Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.

Abstract: An information handling system includes a current detector module and a baseboard management controller (BMC). The current detector module is configured to detect current slew-rate for an element of the information handling system, to determine that the current slew-rate is greater than a current slew-rate threshold, and to provide an indication that the current slew-rate is greater than the current slew-rate threshold on a communication interface. The BMC may enter an item into a log of the information handling system in response to receiving an indication.

Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Example implementations relate to an input/output (I/O) hub. An example I/O hub can include a registered jack (RJ) 12 I/O retail port and a Universal Serial Bus (USB) type-C port to deliver power and communication data to the RJ12 I/O retail port.

Abstract: An electronic device and a method for recognizing accessories that are mounted into a connector of an electronic device are provided. The electronic device includes a housing that includes a first surface that faces in the first direction and a second surface that faces in the second direction, opposite the first direction, a display that is disposed between the first surface and the second surface and is exposed through the first surface, a power supply unit that applies a voltage, and at least one processor that is electrically connected to the display, wherein: the housing includes a universal serial bus (USB) type-C connector, the connector includes a contact substrate that is electrically connected to the processor to detect the insertion of an accessory, and the power supply unit and the processor are electrically connected to a mid plate that is formed in the contact substrate.

Abstract: A power gating circuit is provided. The power gating circuit includes a logic gate group. The power gating circuit also includes a first switching circuit coupled to first and second supply voltages and the logic gate group. The power gating circuit further includes a second switching circuit coupled to the first and second supply voltages and the logic gate group. The first and second supply voltages are supplied to the logic gate group through the first switching circuit based on a voltage select signal. The first and second supply voltages are supplied to the logic gate group through the second switching circuit based on the voltage select signal and a power down signal.

Abstract: An integrated circuit microprocessor device comprises a central processing unit (CPU) and a general purpose input or output subsystem (2) having at least one external connection (4). The external connection is configured to provide an input to or output from the device depending upon an associated setting in the general purpose input or output subsystem. At least one further module on the device is configured to be able to request at least a first or a second task which may control a state of the external connection, the general purpose input or output subsystem being configured, upon receipt of conflicting requests for the first and second tasks, to apply a predetermined priority to allow only one of the tasks to be applied to the external connection.

Abstract: A circuit comprises a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal, and a plurality of clock gating devices. Each of the plurality of clock gating devices comprises a multiplexing device, wherein the modified clock signal is coupled to a selector input of the multiplexing device, and input signal generation circuitry configured to ensure the timing of the transitions on the output are derived purely from the timing of the transitions of the clock and not by the timing of the transition of the first and second inputs of the multiplexer.

Abstract: Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

Abstract: The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and to optimize processor performance based on the connection type. As a non-limiting example, a processor package consistent with the present disclosure may include a central processing unit (CPU) die and a plurality of pins (including two connection detection pins) to connect the package to a motherboard. The CPU die may include connection determination logic and execution policy logic, implemented via processor code (“p-code”), as well as a more typical processor.

Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: Bus enumeration of a switch fabric bus may be performed without assigning bus numbers to unused switch ports and/or corresponding slots to which the unused switch ports are routed. Accordingly, switches coupled to a switch fabric bus in a chassis may link-train with corresponding slots in the chassis in an attempt to establish active connections with devices coupled to the slots. Unused switch fabric bus lanes running from the switches to unused slots may be identified, and the unused switch ports corresponding to the unused switch fabric bus lanes may be disabled. During a subsequent bus enumeration procedure for the switch fabric bus, bus numbers may be allocated to the identified used switch ports (or corresponding used slots) but not to the identified unused switch ports (or corresponding unused slots). The link training, used/unused switch port identification, and bus enumeration may all be performed each time the chassis is reset.

Abstract: A command from a host is received via a port of a storage system. The port is assigned a current port revision identifier. The current port revision identifier of the port is associated with the command. Responsive to a status change associated with the port, an updated port revision identifier is assigned to the port to replace the current port revision identifier of the port and execution of the command is aborted responsive to determining that the current port revision identifier associated with the command is different than the updated port revision identifier of the port.

Abstract: Systems and methods for recording and communicating engine data are provided. One example aspect of the present disclosure is directed to a method for communicating engine data. The method includes receiving data. The method includes separating the data into categories. For one or more categories, the method includes creating a file including the separated data. For one or more categories, the method includes naming the file, at least in part, based on the category and based on a file naming convention. The method includes prioritizing the created files. The method includes transmitting an identification file comprising identification information for a wireless communication unit and the file naming convention. The method includes transmitting the created files based on the priority.

Abstract: A USB-C controller, disposed on an integrated circuit (IC), comprises a first pair of terminals to communicate with a first communication protocol that is other than USB, a second pair of terminals to communicate with a second communication protocol that is other than USB, and a third pair of terminals, each of which is to be coupled to a corresponding SBU1 terminal or SBU2 terminal of a Type-C receptacle. The USB-C controller further includes: a multiplexer to selectively couple the first pair of terminals to the third pair of terminals and the second pair of terminals to the third pair of terminals: and logic to control the multiplexer according to a mode enabled within a configuration channel (CC) signal.

Abstract: A mechanism for augmenting security features associated with internet of things devices located in home and/or office environments is provided. A method can comprise as a function of retrieved data associated with a device, displaying vulnerability data associated with the device; facilitating downloading of resolution data to the device based on the vulnerability data; facilitating reconfiguring of the device based on the resolution data; and allocating reward data representative of a reward to a user device based on the reconfiguring of the device being determined to have completed.

Abstract: Examples are disclosed that relate to computing devices and methods for identifying an approved input device. In one example, a method comprises: receiving a plurality of input signals from a plurality of target user-actuatable input components operated by a user, applying a plurality of rules to the plurality of input signals to generate a confidence score, and comparing the confidence score to a threshold score to determine if the plurality of target user-actuatable input components are associated with an approved input device.

Abstract: An information handling system (IHS) includes a battery management unit (BMU) and an embedded controller (EC). The EC is operable for detecting a trigger for monitoring power consumption in light of a first condition, capturing a state of the IHS, writing data representing the state to a power profile log, annotating the log with an identifier of a point at which logging associated with the first condition begins, obtaining, from the BMU, power data representing an amount of current flowing from or charge delivered by a battery, writing at least some power data to the log, detecting a trigger for ending monitoring associated with the first condition, annotating the log with an identifier of a point at which logging associated with the first condition ends, and generating, dependent on the annotations of the identifiers in the log, a power profile report indicating power consumption associated with the first condition.