Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Abstract: According to one embodiment, at first, a first pattern is formed to an insulating film. Then, a first transparent film is formed on a region of the insulating film, which includes a position where the first pattern is formed. Thereafter, an opaque film which is opaque to light within a visible light region is formed on an entire surface of the insulating film. Then, a second transparent film is generated by selectively oxidizing part of the opaque film in contact with the first transparent film.

Abstract: A light emitting element for flip-chip mounting having a flat mounting surface which allows a decrease in the width of the streets of a wafer. In the light emitting element, the insulating member filling around the bumps and flattening the upper surface is formed with a margin of a region with a width which is equal to or larger than the width of the streets on the dividing lines, so that at the time of dividing the wafer along the dividing lines, the insulating member is not processed, which allows designing of the streets with a small width.

Abstract: Provided is an LED device which is compact while having good luminous efficiency and a focused light distribution. This LED device is provided with: a reflective frame around the outer periphery of the LED device; an LED die which has a transparent insulating substrate, a semiconductor layer formed on the bottom surface of the transparent insulating substrate, and an outer connection electrode disposed on the semiconductor layer; and a fluorescent member which is disposed on at least the top surface of the LED die and which converts the wavelength of the light emitted from the LED die. On the inside of the reflective frame is an inclined surface in contact with the lateral surface of the fluorescent member, and the inclined surface is formed such that the inner diameter of the reflective frame widens from the bottom surface towards the top surface of the LED die. Also provided is a manufacturing method of the LED device.

Abstract: In one aspect, structures are provided comprising: a substrate having a first surface and a second surface; and a polymeric layer disposed on the first surface of the substrate, the polymeric layer comprising a polymer and a plurality of light-emitting nanocrystals; the polymeric layer having a patterned surface, the patterned surface having a patterned first region having a first plurality of recesses and a patterned second region having a second plurality of recesses, wherein the plurality of recesses in each region has a first periodicity in a first direction, and a second periodicity in a second direction which intersects the first direction, wherein the first periodicity of the first region is different from the first periodicity of the second region.

Abstract: A light-emitting device is disclosed and comprises: a transparent substrate; a semiconductor light-emitting stack on the transparent substrate, wherein the semiconductor light-emitting stack comprises a first semiconductor layer close to the transparent substrate, a second semiconductor layer away from the transparent substrate, and a light-emitting layer capable of emitting a light disposed between the first semiconductor layer and the second semiconductor layer; and a bonding layer between the transparent substrate and the semiconductor light-emitting stack, wherein the bonding layer has a gradually changed refractive index, and each of critical angles at the bonding layer and the transparent substrate for the light emitted from the light-emitting layer towards the transparent substrate is larger than 35 degrees.

Abstract: A method of processing a wafer having a device area where a plurality of devices are formed and a peripheral marginal area surrounding the device area on the front side of the wafer is disclosed. The devices are formed in regions defined by division lines. Each device has a plurality of bump electrodes on the front side. A first laser beam is applied through dicing tape from the back side along the boundary between the device area and the peripheral marginal area, with the focal point of the first laser beam set inside the wafer, thereby forming an annular modified layer inside the wafer. A second laser beam is applied through the dicing tape from the back side along each division line with the focal point of the second laser beam set inside the wafer, thereby forming a modified layer inside the wafer along each division line.

Abstract: A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.

Abstract: A method of preparing monoatomic layer black phosphorous by irradiating an ultrasound includes: putting black phosphorus into a solvent and irradiating the ultrasound; recovering a solution from a solution to which the ultrasound is irradiated; and collecting black phosphorus remaining after the solution has been recovered, putting the black phosphorus into a solvent, irradiating the ultrasound, and recovering a solution.

Abstract: A thin film transistor includes: a semiconductor channel film; a gate insulating film on the semiconductor channel film; a gate electrode formed of a laminated film including a first conductive film and a second conductive film on the gate insulating film; an interlayer insulating film covering the semiconductor channel film, the gate insulating film, and the gate electrode; a source electrode formed of a laminated film including a third conductive film and a fourth conductive film formed on the interlayer insulating film; and a drain electrode formed of the third conductive film. A gate wiring is formed of the laminated film including the first conductive film and the second conductive film. A source wiring is formed of the laminated film including the third conductive film and the fourth conductive film. A pixel electrode is formed of the first conductive film. A counter electrode is formed of the third conductive film.

Abstract: Exemplary embodiments of the present invention relate to a method of growing gallium nitride-based semiconductor layers through metal-organic chemical vapor deposition, including disposing a substrate in a chamber, growing a first conductivity-type gallium nitride-based semiconductor layer on the substrate at a first chamber pressure, growing a gallium nitride-based active layer on the first conductivity-type gallium nitride-based semiconductor layer at a second chamber pressure higher than the first chamber pressure, and growing a second conductivity-type gallium nitride-based semiconductor layer on the active layer at a third chamber pressure lower than the second chamber pressure.

Abstract: An electronic part includes a bottom portion of a cavity that has an oscillation device, a ceiling portion so disposed that it faces the bottom portion via the cavity and having holes, a shielding portion that is disposed in the cavity and between the bottom portion of the cavity and the ceiling portion and covers the holes in a plan view viewed in the direction in which the bottom portion of the cavity and the ceiling portion are arranged, and sealing portions that are connected to both the ceiling portion and the shielding portion via the holes and seal the holes.

Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact electrically coupled with the terminal. A first element has a first surface facing the first surface of the substrate, a first conductor at the first surface and a second conductor at a second surface. An interconnect structure may extend through the first element electrically coupling the first and second conductors. An adhesive layer may bond first surfaces of the first element and the substrate, and at least portions of the first conductor and the substrate conductor may be beyond an edge of the adhesive layer. A continuous electroless plated metal region may extend between the first conductor and the substrate conductor.

Abstract: The silicon nitride layer 910 formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer 905 used for the resistor 354, and the silicon nitride layer 910 is provided over the oxide semiconductor layer 906 used for the thin film transistor 355 with the silicon oxide layer 909 serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer 905 than into the oxide semiconductor layer 906. As a result, the resistance of the oxide semiconductor layer 905 used for the resistor 354 is made lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.

Abstract: Methods for self-aligned multiple patterning including controlled slimming of features during spacer layer deposition. Multiple spacer layer deposition process conditions produce a balance between controlling the damage to the features and increasing production throughput.

Abstract: After oxidizing a sacrificial semiconductor layer composed of silicon germanium that is located over an insulator layer to form a germanium-enriched region located within a first end of the sacrificial semiconductor layer and having a greater germanium concentration than a remaining portion of the sacrificial semiconductor layer, the remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the germanium-enriched region that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.

Abstract: According to one embodiment, a method for producing a semiconductor device includes forming a base film above a semiconductor substrate, forming a core above the base film, forming a side wall film on a side face of the core, and replacing at least part of the side wall film with a metal film by performing plating processing.

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract: An image sensor including a semiconductor layer. A light absorber layer couples with the semiconductor layer at a pixel of the image sensor and absorbs incident light to substantially prevent the incident light from entering the semiconductor layer. The light absorber layer heats a depletion region of the semiconductor layer in response to absorbing the incident light, creating electron/hole pairs. The light absorber layer may include one or more narrow bandgap materials.