Abstract: A surface light source device is provided that has high light extraction efficiency and high mechanical strength and can suppress a change in color tone at different viewing angles. To that end, the surface light source device includes: an organic EL element including a luminescent layer; and a light-emitting surface structure layer that is disposed in contact with one of the surfaces of the organic EL element and defines a concave-convex structure on the surface on the device light-emitting surface side. The concave-convex structure includes a plurality of concave portions having oblique surfaces and flat portions disposed around the concave portions. The surface light source device further includes a diffusing member on which the light emitted from the luminescent layer is incident, the diffusing member allowing the incident light to pass therethrough or reflecting the incident light in a diffused manner.

Abstract: According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: A method and apparatus provide for a roughened back surface of a semiconductor absorber layer of a photovoltaic device to improve adhesion. The roughened back surface may be achieved through an etching process.

Abstract: A semiconductor wafer with (100) plane orientation has two orthogonal cleavage directions. A notch is provided so as to indicate one of these directions. During irradiation with a flash, the semiconductor wafer warps about one of two radii at an angle of 45 degrees with respect to the cleavage directions such that the upper surface thereof becomes convex, and the opposite ends of the other radii become the lowest position. Eight support pins in total are provided in upright position on the upper surface of a holding plate of a susceptor while being spaced at intervals of 45 degrees along the same circumference. The semiconductor wafer is placed on the susceptor such that any of the support pins supports a radius at an angle of 45 degrees with respect to a cleavage direction.

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

Abstract: The invention is directed to an integrated polarized light emitting diode device that has a light emitting diode, a metal grating, an oxide layer, and a built-in photonic crystal rotator. Additional teachings include a method for making the integrated polarized light emitting diode, a method for improving the polarization selectivity and energy efficiency of a light emitting diode, and a method for rotating polarization of a light emitting diode.

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact.

Abstract: The invention relates to a light-emitting semiconductor component, comprising—a first semiconductor body (1), which comprises an active zone (11) in which during the operation of the light-emitting semiconductor component electromagnetic radiation is generated, at least some of which leaves the first semiconductor body (1) through a radiation exit surface (1a), and—a second semiconductor body (2), which is suitable for converting the electromagnetic radiation into converted electromagnetic radiation having a longer wavelength, wherein—the first semiconductor body (1) and the second semiconductor body (2) are produced separately from each other, —the second semiconductor body (2) is electrically inactive, and—the second semiconductor body (2) is in direct contact with the radiation exit surface (1a) and is attached there to the first semiconductor body (1) without connecting means.

Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

Abstract: The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a horizontal surface. The method includes forming an interconnect structure over the horizontal surface of the substrate. The forming the interconnect structure includes forming an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The forming the interconnect structure includes forming a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.

Abstract: The memory device is provided to include a substrate, a plurality of stack structures, conductive pillars, charge storage layers, and third conductive layers. The stack structures are arranged along a first direction and extend along a second direction, wherein each stack structure includes a plurality of first conductive layers and a plurality of dielectric layers that are alternately stacked along a third direction. Each conductive pillar is located on the substrate between two adjacent stack structures. Each charge storage layer is disposed between the stack structures and the conductive pillars. Each third conductive layer extending along the first direction overlaps the stack structures in a plurality of overlapped regions and covers a portion of top parts of the stack structures and the conductive pillars. An air gap is formed along the third direction in each overlapped region where the stacked structures and the third conductive layers overlap.

Abstract: A group III nitride semiconductor light-emitting element having a pn junction hetero structure composed of: an n-type aluminum gallium indium nitride layer; a light-emitting layer disposed contacting the n-type aluminum gallium indium nitride layer and including a gallium indium nitride layer containing crystals having a larger lattice constant than the n-type aluminum gallium indium nitride layer; and a p-type aluminum gallium indium nitride layer provided on the light-emitting layer. Further, the relative atomic concentrations of donor impurities at either interface of the light-emitting layer and within respective layers of the light-emitting element are specified herein.

Abstract: The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor. The other of the source and drain electrodes of the second transistor is electrically connected to the first wiring, and a gate electrode of the second transistor is electrically connected to one of electrodes of a second capacitor and a fifth wiring. The other electrode of the first capacitor is electrically connected to a third wiring, and the other electrode of the second capacitor is eclectically connected to a fourth wiring.

Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.