Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.

Abstract: In a light-emitting element 1, a light-emitting layer 4, a second conductivity type semiconductor layer 5, a transparent electrode layer 6, a reflecting electrode layer 7 and an insulating layer 8 are stacked in this order on a first conductivity type semiconductor layer 3, while a first electrode layer 10 and a second electrode layer 12 are stacked on the insulating layer 8 in an isolated state.

Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.

Abstract: Disclosed are a non-polar hetero substrate, a method for manufacturing the same, and a nitride-based light emitting device using the same. The non-polar hetero substrate includes a non-polar base substrate, a nitride base layer disposed on the substrate, a defect reduction layer disposed on the nitride base layer, the defect reduction layer including a plurality of air gaps, and a nitride semiconductor layer disposed on the defect reduction layer.

Abstract: An LED package structure includes a substrate, two electrodes engaged in the substrate, an LED chip, a reflective cup and an encapsulation. The substrate includes a first surface and a second surface opposite to the first surface. Each of the electrodes defines a groove. The grooves surrounding the LED chip. The LED chip is mounted on one of the electrodes and electrically connected to the two electrodes. The reflective cup is mounted on the substrate and surrounds the LED chip. The encapsulation covers the LED chip and extends in the grooves of the electrodes to prevent water/moisture from entering the LED chip.

Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.

Abstract: A resist layer (46a) including a thick film section (47a), which is relatively thick, at one side thereof, and a thin film section (47b), which is relatively thin, at the other side thereof is formed using a multiple-tone mask. A gate electrode (15a) is formed at a place where it will be provided on a semiconductor layer (12a) so as to be narrower than the resist layer (46a), by executing isotropic etching to a conductive film (44) formed in advance using the resist layer (46a) as a mask, in order to form overhang portions (48) on the resist layer (46a) at both sides of the gate electrode (15a). Then, the entire thin film section (47b) is removed, the thick film section (47a) is made thinner, and impurities are implanted into the semiconductor layer (12a) using the remaining resist layer (46a) and the gate electrode (15a) as masks.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal.

Abstract: A phosphor layer attaching kit includes a phosphor layer and a silicone pressure-sensitive adhesion composition for attaching the phosphor layer to an optical semiconductor element or an optical semiconductor element package. A percentage of the peel strength of the silicone pressure-sensitive adhesion composition is 30% or more.

Abstract: The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected to an adherend, the film for flip chip type semiconductor back surface containing an inorganic filler in an amount within a range of 70% by weight to 95% by weight based on the whole of the film for flip chip type semiconductor back surface.

Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.

Abstract: According to embodiments, a semiconductor device includes a semiconductor substrate and an element isolation insulating film which isolates a element formation region in a surface portion of the semiconductor substrate. A depletion-type channel region of a first conductivity type is formed in an inner region which is in the element formation region of the semiconductor substrate and is a predetermined distance or more away from the element isolation insulating film. A gate electrode is formed above the element formation region with a gate insulating film located in between in such a manner as to traverse over the channel region and to overlap with portions of the element isolation insulating film which are located on both sides of the element formation region. Source/drain regions of the first conductivity type are formed in the channel region respectively on both sides of the gate electrode.

Abstract: According to one embodiment, a semiconductor light emitting element includes: a first conductive pillar extending in a first direction; a second conductive pillar extending in the first direction; a first semiconductor layer of a first conductivity type provided on the first conductive pillar; a light emitting layer provided on the first semiconductor layer; a second semiconductor layer of a second conductivity type provided on the light emitting layer and on the second conductive pillar; a sealing unit covering a side surface of the first conductive pillar and a side surface of the second conductive pillar; and a light transmissive layer provided on the second semiconductor layer and having light transmissivity, a hardness of an upper surface portion of the light transmissive layer being higher than a hardness of a lower portion between the upper surface portion and the second semiconductor layer.

Abstract: A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.

Abstract: According to one embodiment, a semiconductor light emitting device includes first and second columnar units, a wavelength conversion layer, a light emitting unit, a resin unit and an intermediate layer. The first columnar unit extends in a first direction. The second columnar unit is provided apart from the first columnar unit, and extends in the first direction. The wavelength conversion layer is provided apart from the first and second columnar units in the first direction. The light emitting unit includes first and second semiconductor layers, and a light emitting layer configured to emit a first light. The resin unit covers side surfaces along the first direction of the first and second columnar units and the light emitting unit, and a surface of the light emitting unit. The intermediate layer includes first and second portions, and has a thickness thinner than a peak wavelength of the first light.

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract: A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract: A semiconductor light emitting device includes a semiconductor lamination including a p-type semiconductor layer, an active semiconductor layer, and an n-type semiconductor layer; opposing electrode structure including a first electrode structure formed above the p-type semiconductor layer, and a second electrode structure formed above the n-type semiconductor layer; and brightness grade producing structure including a surface layer of at least one of the p-type semiconductor layer and the n-type semiconductor layer and producing brightness grade gradually changing from one edge to opposite edge of light output plane.