Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.

Abstract: A semiconductor device includes: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate below and adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field. The shielding region has a higher net doping concentration than the current-conduction region, and has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region. The current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, and L/d is in a range of 1 to 10.

Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer.

Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

Abstract: A method of forming a phase change random access memory (PCRAM) device includes forming a phase change element over a bottom electrode and a top electrode over the phase change element, forming a protection layer around the phase change element, and forming a nitrogen-containing sidewall spacer layer around the protection layer after forming the protection layer.

Abstract: A semiconductor device of an embodiment includes: a silicon carbide layer including a first silicon carbide region of n-type containing one metal element selected from a group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) and a second silicon carbide region of p-type containing the metal element; and a metal layer electrically connected to the first silicon carbide region and the second silicon carbide region. Among the metal elements contained in the first silicon carbide region, a proportion of the metal element positioned at a carbon site is higher than a proportion of the metal element positioned at an interstitial position. Among the metal elements contained in the second silicon carbide region, a proportion of the metal element positioned at an interstitial position is higher than a proportion of the metal element positioned at a carbon site.

Abstract: A semiconductor device includes an active area structure, at least one gate and at least one isolation structure. The active area structure is arranged along a first direction. The at least one gate is arranged above the active area structure and along a second direction. The second direction is different from the first direction. The at least one isolation structure is arranged in the active area structure. A length of the at least one isolation structure is shorter than a width of the active area structure in the second direction.

Abstract: Embodiments of the present provide a connection structure and a manufacturing thereof, an array substrate and a manufacturing method thereof, the manufacturing method of the connection structure includes: forming a first insulating layer on a base substrate forming a mask layer having a first opening on a side of the first insulating layer away from the base substrate; forming a second insulating layer op a side of the mask layer away-from the first insulating layer; forming a second opening exposing the first opening in the second insulating layer by one patterning process, and forming a third opening in the first insulating layer.

Abstract: A wide gap semiconductor device has: a drift layer 12 using a first conductivity type wide gap semiconductor material; a well region 20, being a second conductivity type and provided in the drift layer 12; a polysilicon layer 150 provided on the well region 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.

Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes: a base substrate; a first sub-pixel disposed on the base substrate and including a first light-emitting device configured to emit visible light for display operation; a second a light-emitting device overlapped with the first light-emitting device in a direction perpendicular to the base substrate and configured to emit infrared light; and a first photosensitive device disposed on the base substrate and configured to sense light obtained after the infrared light is reflected.

Abstract: A method of manufacturing a display device includes preparing a carrier substrate, forming a first substrate layer on the carrier substrate, forming a first, second, and third through holes in the first substrate layer, forming a first intermediate conductive layer having a first exposed portion and a second exposed portion, forming a second intermediate conductive layer having a third exposed portion, forming a second substrate layer on the first substrate layer to cover the first intermediate conductive layer and the second intermediate conductive layer, forming a fourth through hole in the second substrate layer, forming a wiring on the second substrate layer, separating the first substrate layer from the carrier substrate, arranging a first electronic device on a surface of the first substrate layer, and arranging a second electronic device on the surface of the first substrate layer.

Abstract: The present disclosure provides an array substrate, a display panel, and a manufacturing method of the array substrate. The display panel includes the array substrate. The array substrate includes a planarization layer provided with a groove surrounding a display area in a non-display area, the groove includes a bottom surface and two side inclined planes, and an included angle (taper angle) between the bottom surface and the side inclined planes ranges from 30° to 45°. When manufacturing the groove, a plurality of side inclined sub-planes are manufactured at intervals and connected to each other to form the side inclined planes.

Abstract: The present disclosure relates to an array substrate, a manufacturing method thereof, and a display panel, the array substrate including: a substrate, and a low temperature polysilicon layer, an inorganic film group layer, and a source/drain layer disposed on the substrate in sequence. The substrate includes a display region, the low temperature polysilicon layer located at the display region, the inorganic film group layer provided with a through hole, and an angle between a sidewall and a bottom wall of the through hole is not less than 100 degrees; the source/drain layer covering the sidewall and the bottom wall of the through hole to be connected to the low temperature polysilicon layer.

Abstract: A display panel includes a substrate, a first gate-electrode metal layer, a first organism, and a second organism. The first organism is disposed on one surface of the first gate-electrode metal layer near the substrate in order that a bending stress is released. The second organism is disposed on one surface of the first gate-electrode metal layer away from the substrate in order that the bending stress is released. Organisms are disposed above a metal trace and below the metal trace, so that a stress which occurs in inorganic layers can be released through the organisms when the display panel is being bent.

Abstract: A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region.

Abstract: An embodiment relates to a method and manufacture of robust, high-performance devices. The method comprises preparing a unit cell of a Silicon Carbide (SiC) substrate comprising a first conductivity type substrate and a first conductivity type drift layer; forming a second conductivity type well region; forming a first conductivity type source region within the second conductivity type well region; and forming a second conductivity type shield region surrounding the first conductivity type source region. The second conductivity type shield region formed comprises a portion of the second conductivity type shield region located on a SiC surface.

Abstract: A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) transistor and a semiconductor can reduce the size of the entire power block and can decrease costs by preventing formation of an edge termination region between adjacent device tips or ends along a width direction when the corresponding LDMOS transistor cell has a limited width and the LDMOS transistor is a multi-finger LDMOS transistor.

Abstract: A power semiconductor device includes: a semiconductor body having a front side surface and a drift region having first conductivity type dopants; and an edge termination region that includes a part of the drift region and a first semiconductor region extending along the front side surface. The first semiconductor region includes dopants of both conductivity types and forms a continuous pn-junction with the drift region. An integrated vertical dopant concentration of the second conductivity type dopants is higher than an integrated vertical dopant concentration of the first conductivity type dopants within the first semiconductor region.