Patents Examined by Fernando Hidalgo
  • Patent number: 10998052
    Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
  • Patent number: 10998018
    Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shubham Ranjan, Parvinder Kumar Rana, Janardhan Achanta, Manish Chandra Joshi
  • Patent number: 10998029
    Abstract: Methods, systems, and devices for low voltage ferroelectric memory cell sensing are described. As part of an access operation for a memory cell, gates of two cascodes may be biased to compensate for associated threshold voltages. An extracted signal corresponding to a charge stored in the memory cell may be transferred through a first cascode to charge a first capacitor. Similarly, a reference signal developed at a dummy digit line may be transferred through a second cascode to charge a second capacitor. By comparing the reference signal developed at the dummy digit line to the extracted signal from the memory cell, the effect of variations in memory cell performance on the sense window may be reduced. Additionally, based on biasing the gates of the cascodes, the difference between the signals compared at the sense component may be low compared to other sensing schemes.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10996856
    Abstract: The present disclosure involves a hardware-supported 3D-stacked NVM data compression method and system, involving setting a first identifier to mark a compression state of written-back data, the method at least comprising steps of: dividing the written-back data into a plurality of sub-blocks and acquiring a plurality of first output results through OR operations among the sub-blocks, respectively, or acquiring a plurality of second output results through exclusive OR operations among the sub-blocks, and determining a compression strategy for the written-back data based on the first output results or the second output results; and setting a second identifier to mark a storing means of the written-back data so that the second identifier is in pair with the first identifier, and configuring a storage strategy for the written-back data that includes at least rotating the second identifier.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: May 4, 2021
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Haikun Liu, Xiaofei Liao, Hai Jin, Yuanyuan Ye
  • Patent number: 10998047
    Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 4, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10998319
    Abstract: Provided is a memory structure including a substrate having a memory region and a peripheral region, a capacitor array, a transistor array, bit lines, and contacts. The capacitor array is on the substrate in the memory region. The transistor array is on and electrically connected to the capacitor array. The bit lines are extended along a row direction in parallel with each other on the transistor array, and are electrically connected to the transistor array. Each of the contacts is connected to one of the bit lines and a conductive device at the substrate in the peripheral region. Each of the contacts includes a first portion, a second portion, and a third portion. The second portion is between the first portion and the third portion. The third portion is electrically connected to the conductive device. Distances between each of the third portions and the memory region are the same.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 4, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 10991420
    Abstract: A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Patent number: 10984869
    Abstract: A memory device includes: a memory block including a plurality of main pages and a dummy page; a peripheral circuit for performing a normal program operation on the plurality of main pages and a dummy program operation on the dummy page in a program operation, and reading data stored in the dummy page and the plurality of main pages in a read operation; and control logic for controlling the peripheral circuit to program, to the dummy page, the same data as first logical page data of a first main page among the plurality of main pages in the program operation.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Ho Kim, Jong Han Ahn, Seong Cheon Yu
  • Patent number: 10978152
    Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 13, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 10971219
    Abstract: A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 6, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Patent number: 10971509
    Abstract: A semiconductor memory device according to the present technology includes a stack body including a lower conductive pattern and an upper conductive pattern stacked apart from each other in a first direction, and at least one intermediate conductive pattern disposed between the lower conductive pattern and the upper conductive pattern, a contact plug connected to the lower conductive pattern and extending in the first direction, and at least one lower dummy plug overlapping the lower conductive pattern.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae Taek Kim
  • Patent number: 10971231
    Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 6, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 10971220
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10964401
    Abstract: An arrangement is described used to throttle data in a connected computer device having a device configured to transmit and receive data from a host, the device comprising, a device controller configured to interact with at least memory array and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 10964712
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
  • Patent number: 10956832
    Abstract: A method is provided to produce training data set for training an inference engine to predict events in a data center comprising: producing probe vectors corresponding to components of a data center, each probe vector including a sequence of data elements, one of the probe vectors indicating an event at a component and at a time of the event; and producing at a master device a set of training snapshots, wherein each training snapshot includes a subsequence of data elements that corresponds to a time increment that matches or that occurred not later than the indicated time of occurrence of the event.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 23, 2021
    Assignee: Platina Systems Corporation
    Inventors: Frank Szu-Jen Yang, Ramanagopal V. Vogety, Sharad Mehrotra
  • Patent number: 10950790
    Abstract: A two-terminal memory device and methods for its use are provided. In the device, a bottom electrode is electrically continuous with a first operating terminal, and a control gate electrode is electrically continuous with a second operating terminal. A stack of insulator layers comprising a hopping conduction layer and a tunnel layer is contactingly interposed between the bottom electrode and the control gate electrode. The tunnel layer is thinner than the hopping conduction layer, and it has a wider bandgap than the hopping conduction layer. The hopping conduction layer consists of a material that supports electron hopping transport.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: March 16, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Matthew Marinella, Sapan Agarwal
  • Patent number: 10949745
    Abstract: A cognitive learning device includes inputs with each including an input path having a transistor device having a storage capacity. A circuit is responsive to the inputs and selects an input set in accordance with a current task, wherein the input set selected modifies a characteristic of the transistor device of one or more corresponding input paths to bias the input set for selection for subsequent accesses.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10942873
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Patent number: 10943667
    Abstract: A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi, Wei-Chang Zhao