Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

Abstract: Various example embodiments provide for handling a power-loss reset (PLRESET) event in a memory system, such as a memory sub-system, with a technique that mitigates the risk of a good block being marked as bad, a memory die being retired prematurely, or both.

Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

Abstract: A method and an apparatus for memory testing are provided. The method includes following steps: after multiple dies are idle for a first time, performing a first stage test on the dies, and setting multiple flags corresponding to the dies that fail the first stage test to a first logic level; after the dies are idle for a second time, performing a second stage test on the dies, and regarding the dies that pass the second stage test and have the corresponding flags set to the first logic level as suspected good dies and keeping the suspected good dies idle; and after the suspected good dies are idle for a third time, performing a third stage test on the suspected good dies.

Abstract: Example memory devices, systems, and methods for reducing verify operation time in memory devices are disclosed. One example method includes performing, based on one of 2N pieces of N-bits data, a first programming operation of the target memory cell to program the target memory cell into an intermediate threshold voltage range P 1 I of a first set of 2N?1 threshold voltage ranges { P 1 0 , P 1 1 , … , P 1 2 N - 2 } , where P 1 2 N - 2 ? and ? P 1 2 N - 3 share a same verify voltage.

Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.

Abstract: Disclosed are a data inversion encoding circuit, an eFLASH memory device and an operation method thereof. The data inversion encoding circuit includes a count and comparison circuit, receiving data with plural bits, counting numbers of 0 and 1 in the bits, and outputting a selection signal when number of 0 is larger than number of 1; an inverter, receiving the data and outputting bit inversion data; and a selection circuit, receiving the data and the bit inversion data, and selecting the data or the bit inversion data based on the selection signal. The bit inversion data is output when number of 0 is larger than number of 1.

Abstract: The present application provides methods of operating memories, memories and memory systems. An example method includes: at a first reading period, performing a sensing operation on memory cells based on a first read voltage, a sensing development duration for the sensing operation performed on the memory cells being not shorter than a first development duration. Based on different sensing development durations, at a first sensing period and a second sensing period of the first reading period, a number of first memory cell, a number of second memory cell and a number of third memory cell are obtained. Based on the number of first memory cell, the number of second memory cell and the number of third memory cell, a valley voltage between a first threshold voltage distribution range and a second threshold voltage distribution range is determined.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells each connected to a bit line pair; and a write circuit that brings a low potential-side bit line to a negative potential in response to a negative potential boost signal. At the data read operation, a word line is activated after a lapse of a first predetermined time from a transition of an input clock signal, to read the memory value of the memory cell. At the data write operation, the word line is activated after a lapse of a second predetermined time longer than the first predetermined time from a transition of the input clock signal, and the negative potential boost signal is activated after a lapse of a third predetermined time longer than the first predetermined time.

Abstract: A memory device comprising a stacking structure including a plurality of electrodes and an insulation layer between the plurality of electrodes. The stacking structure has a recess portion corresponding to the plurality of electrodes or the insulation layer at a side surface of the stacking structure. The memory device also comprising a resistance variable layer on the side surface of the stacking structure having the recess portion, and includes a portion extending in an extension direction crossing the stacking structure. The resistance variable layer includes a first portion including a first expanded portion along a recess surface of the recess portion, a second portion including a second expanded portion along the recess surface of the recess portion on the first portion, and a third portion on the second portion. The second portion has a resistance smaller than a resistance of the first portion.

Abstract: A memory includes first magnetic-members extending in a first direction and having a first and s second end portions. Second magnetic-members are provided corresponding to the first magnetic-members, and extend in the first direction from an inside of cylinders of the first magnetic-members on a side of the second end portions. Third magnetic-members are provided above the second magnetic-members corresponding to the first magnetic-members, and are electrically disconnected from the second magnetic-members. First wires extend in a second direction, are arranged in a third direction intersecting the first and the second directions, and are electrically connected to the third magnetic-members arranged in the second direction. A fourth magnetic-member is provided around the second end portions of the first magnetic-members, and is electrically disconnected from the second and third magnetic-members. Second wires are provided on a side of the first end portions of the first magnetic-members.

Abstract: Provided are a low dropout (LDO) regulator controlling operation biasing of a transistor connected to an output node to have a wide bandwidth and provide a stable voltage at a fast speed, and a memory device including the LDO regulator. The LDO regulator includes a first low voltage transistor in which a first terminal thereof is connected to an output node configured to provide an output voltage to a load and a second terminal thereof is connected to a first node, an operational amplifier configured to compare a reference voltage with the output voltage and output the comparison result to a gate terminal of a first low voltage transistor, and an operation biasing control circuit connected to the output node and the first node, and including at least one high voltage transistor.

Abstract: Disclosed is an operation method of a controller which communicates with a plurality of memory devices. The method includes receiving a first reception signal, a second reception signal, and a data strobe signal, respectively, generating a first delay signal by performing first and second per-pin delay locked loop (ppDLL) operations on the first and second reception signals based on a rising edge of the data strobe signal, respectively, and generating first and second correction signals by performing first and second per-pin duty cycle correction (ppDCC) operations on the first and second delay signals based on a falling edge of the data strobe signal, respectively. Rising edges of the first and second correction signals are aligned with the rising edge of the data strobe signal, and first and second falling edges of the first correction signals are aligned with the falling edge of the data strobe signal.

Abstract: A method of fabricating a device includes forming a multi-layer stack comprising a plurality of electrode layers and a first dielectric layer comprising a non-linear polar material. The method further comprises forming a second dielectric layer on the multi-layer stack, annealing the multi-layer stack, and forming a transistor above a second substrate. A third dielectric layer is formed above the transistor. The second dielectric layer can be bonded with the third dielectric layer and the multi-layer stack can be etched to form a capacitor and a plate electrode connected with the capacitor. An electrode structure can be formed, where at least a portion of the electrode structure extends through the plate electrode and couples with a terminal of the transistor.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of bit lines, a source line, a plurality of NAND strings, a first and a second sub block, a first word line group included in the first sub block, a second word line group included in the second sub block, and a dummy word line located between the first and second sub blocks; and a control circuit capable of applying predetermined voltages to the first word line group, the second word line group, and the dummy word line. When a specific word line belonging to the first word line group is selected for the execution of a write operation, a voltage higher than voltages applied to an unselected word line belonging to the first word line group and the second word line group is applied to the dummy word line.

Abstract: An integrated circuit includes a substrate; a bit cell array including bit cells on the substrate; a frontside wiring layer above the substrate in a vertical direction with respect to a front side of the substrate, the frontside wiring layer including local word lines connected to the bit cells; a row decoder configured to provide word line signals for driving the bit cell array; a backside wiring layer on a backside of the substrate, the backside wiring layer including backside wiring lines configured to receive the word line signals from the row decoder; and a word line rebuffer configured to provide the word line signals received from the backside wiring lines to the local word lines.

Abstract: An apparatus comprising a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line. The apparatus further comprises a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, and wherein the capacitor includes at least four stable states. In at least one example, the capacitor has a first polarization loop and a second polarization loop, wherein the second polarization loop is within the first polarization loop.

Abstract: A method includes determining that a power event involving a memory sub-system has occurred. The method further including in response to the determination that the power event has occurred, generating signaling indicative of performance of an operation to provide power to a plurality of memory components of the memory sub-system, where the signaling indicative of performance includes a power control signal is applied to a first memory component at a first time, and is applied to a second memory component at a second time that is subsequent to the first memory component entering a steady state.

Abstract: A computation in memory system includes a plurality of block pairs. Each of the plurality of block pairs includes two types of blocks, and each of the two types of blocks includes a plurality of operation units. Each of the plurality of operation units includes a static random access memory, an AND gate, a NOR gate and a capacitor. The capacitor is electrically connected to the NOR gate, the NOR gate is electrically connected to the AND gate, the AND gate is electrically connected to the static random access memory, and the static random access memory performs memory reading and writing functions.