Patents Examined by Fernando Hidalgo
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Patent number: 12217806Abstract: Methods, systems, and devices for threshold voltage scans are described. A memory device may receive a configuration for scanning a memory array during a scanning procedure. The memory device may read, during the scanning procedure, one or more memory cells of the memory array using a first voltage value that is indicated by the configuration. The memory device may store, during the scanning procedure, a first value in a first counter in response to reading the one or more memory cells of the memory array. The memory device may determine whether to terminate the scanning procedure in response to one or both of determining that the first quantity of memory cells satisfies a threshold quantity of memory cells or determining that the first voltage value satisfies a threshold voltage value to be scanned.Type: GrantFiled: July 22, 2022Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Aniello Palomba, Ciro Feliciano, Antonio Imperiale
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Patent number: 12217785Abstract: An integrated circuit includes an array of word lines, and an array of memory cells configured to receive selection signals from the array of word lines. Each memory cell in the array of memory cells is connected to one or more data lines in a set of data lines. The integrated circuit also includes a read-write driver which is connected to the set of data lines and is configured to receive a flip-refresh control signal. The read-write driver has a catch circuit configured to store a first bit value related to a stored bit value in a selected memory cell. The read-write driver is configured to store into the selected memory cell a second bit value which is a bit inversion of the stored bit value.Type: GrantFiled: January 27, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Yen Chuang, Katherine H. Chiang
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Patent number: 12217826Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.Type: GrantFiled: February 16, 2024Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Sai-Hooi Yeong, Chi On Chui
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Patent number: 12217792Abstract: A memory circuit includes a set of memory cells configured to store data, and a local input output (LIO) circuit coupled to a global bit line and the set of memory cells. The LIO circuit includes a sense amplifier, a driver circuit and a booster circuit. The sense amplifier is configured to sense a first signal in response to at least a sense amplifier signal. The first signal corresponds to a value of the data stored in the set of memory cells. The driver circuit is configured to generate a global bit line signal in response to at least the first signal or an inverted first signal. The booster circuit is coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal.Type: GrantFiled: May 13, 2022Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Atul Katoch, Sahil Preet Singh
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Patent number: 12205665Abstract: A 3D memory device is provided. The 3D memory device includes a first logic base layer, a second layer, and a third layer. The first logic base layer comprises a first type DEMUX, a plurality of second type DEMUXs coupled to the first type DEMUX, a first type MUX, and a plurality of second type MUXs coupled to the first type MUX. The second layer comprises a first group of memory units. Each of the first group of memory units is respectively coupled to a corresponding DEMUX of the plurality of second type DEMUXs and a corresponding MUX of the plurality of second type MUXs. The third layer comprises a second group of memory units. Each of the second group of memory units is respectively coupled to a corresponding DEMUX of the plurality of second type DEMUXs and a corresponding MUX of the plurality of second type MUXs.Type: GrantFiled: January 17, 2023Date of Patent: January 21, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Murat Kerem Akarvardar, Xiaochen Peng
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Patent number: 12198747Abstract: A memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.Type: GrantFiled: February 2, 2023Date of Patent: January 14, 2025Assignee: SK hynix Inc.Inventors: Sang Hyun Ku, Do Hong Kim, Min Ho Seok, Duck Hwa Hong, So Yoon Kim
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Patent number: 12200942Abstract: A method of writing data to a Ferroelectric-FET (FeFET) based non-volatile memory device can be provided by applying a voltage pulse at a write voltage level with a write polarity at a gate electrode of a FeFET device with reference to a source electrode of the FeFET device, as a write operation to the FeFET device to establish a state for the FeFET device, changing the voltage pulse, directly after the write operation, to a non-zero bias voltage level with a bias polarity that is opposite to the write polarity, at the gate electrode with reference to the source electrode for a delay time to reduce neutralization of a trap state associated with the write operation of the FeFET device, and changing the voltage pulse, after the delay time, to a read voltage level as a read operation to the FeFET device to determine the state of the FeFET device established during the write operation.Type: GrantFiled: December 8, 2022Date of Patent: January 14, 2025Assignee: Georgia Tech Research CorporationInventors: Asif Khan, Winston Chern, Yuan-Chun Luo, Nujhat Tasneem, Zheng Wang, Shimeng Yu
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Patent number: 12198784Abstract: A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.Type: GrantFiled: March 1, 2023Date of Patent: January 14, 2025Assignee: SK hynix Inc.Inventors: Jung Taek You, Sang Sic Yoon, Kyu Dong Hwang, Chae Sung Lim, Saeng Hwan Kim, Hong Joo Song
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Patent number: 12189996Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.Type: GrantFiled: October 19, 2023Date of Patent: January 7, 2025Assignee: Micron Technology, Inc.Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
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Patent number: 12189951Abstract: A memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determine an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range can be determined based on the anchor read reference voltage. A second best read offset of a second best read reference voltage with respect to the second read reference voltage can be determined by searching in the first scan range. A reading process can be performed to read the page from the set of MLCs based on the first and second best read reference voltages.Type: GrantFiled: January 19, 2023Date of Patent: January 7, 2025Assignee: Yangtze Memory Technologies Co., Ltd.Inventor: Yufei Feng
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Patent number: 12190959Abstract: Aspects of the present disclosure configure a memory sub-system processor to manage memory erase operations. The processor accesses a configuration register to identify a quantity of memory slices to erase. The processor divides a set of memory components into a plurality of portions based on the identified quantity of memory slices to erase and performs one or more read operations in association with the memory sub-system between erasure of each of the plurality of portions of the set of memory components.Type: GrantFiled: August 23, 2022Date of Patent: January 7, 2025Assignee: Micron Technology, Inc.Inventor: Phil Reusswig
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Patent number: 12183717Abstract: An information handling system includes a first z-axis compression connector having a first depth, a first memory module, a second z-axis compression connector having a second depth that is greater than the first depth, a second memory module, and a printed circuit board. A first side of the first compression connector is affixed to the printed circuit board at a first location and a first surface of a first memory circuit board of the first memory module is affixed to a second side of the first compression connector. A first side of the second compression connector is affixed to the printed circuit board at a second location adjacent to the first location and the first side of a second memory circuit board of the second memory module is affixed to a second side of the second compression connector.Type: GrantFiled: July 12, 2022Date of Patent: December 31, 2024Assignee: Dell Products L.P.Inventors: Arnold Thomas Schnell, Joseph Daniel Mallory
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Patent number: 12183422Abstract: A memory device and an in-memory search method thereof are provided. The in-memory search method includes: providing, in a first stage, a first voltage or a second voltage to a word line of at least one target memory cell according to a logical status of searched data, and reading a first current; providing, in a second stage, a third voltage or a fourth voltage to the word line of the at least one target memory cell according to the logical status of the searched data, and reading a second current; and obtaining a search result according to a difference between the second current and the first current.Type: GrantFiled: February 9, 2023Date of Patent: December 31, 2024Assignee: MACRONIX International Co., Ltd.Inventors: Po-Hao Tseng, Feng-Min Lee, Tian-Cih Bo
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Patent number: 12170125Abstract: Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.Type: GrantFiled: July 31, 2023Date of Patent: December 17, 2024Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Chien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hua-Tai Shieh
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Patent number: 12170104Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.Type: GrantFiled: August 29, 2023Date of Patent: December 17, 2024Assignee: Sony Group CorporationInventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
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Patent number: 12165707Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, a plurality of static random access memory (SRAM) cells arranged in a second memory array, and a controller configured to access the first memory array and the second memory array with different access rate. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, a ferroelectric layer over the gate electrode, a first electrode over the gate electrode, and a second electrode over the first electrode. The ferroelectric layer is formed between the first and second electrodes.Type: GrantFiled: October 24, 2023Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin
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Patent number: 12160996Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.Type: GrantFiled: October 9, 2023Date of Patent: December 3, 2024Assignee: SUNRISE MEMORY CORPORATIONInventors: Christopher J. Petti, Vinod Purayath, George Samachisa, Wu-Yi Henry Chien, Eli Harari
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Patent number: 12154613Abstract: Methods, systems, and devices for power-efficient access line operation for memory are described. A memory device may drive a voltage pulse on a first word line included in a set of word lines that is coupled with a master word line. The memory device may then a voltage pulse on a second word line included in the set of word lines coupled with the master word line. In between driving the voltage pulse on the first word line and driving the voltage pulse on the second word line, the memory device may maintain a voltage on the master word line below a threshold level.Type: GrantFiled: May 10, 2022Date of Patent: November 26, 2024Assignee: Micron Technology, Inc.Inventors: Martin Brox, Manfred Hans Plan
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Patent number: 12154628Abstract: A peripheral circuit of a memory device is configured to: in the process of programming a first physical page, perform a programming verification to a programming corresponding to the 2(N?M) th memory state; when the program verification of the 2(N?M) th memory state is passed, identifiers corresponding to the 1st to 2(N?M) th memory states stored by the main latch are made different from those corresponding to the 2(N?M)+1st to 2N th memory states; release at least one of the N page latches to cache program data of at least one logical page of the N logical pages of a second physical page; and the programming data of one logical page in the N logical pages of the second physical page is stored in a released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N?2).Type: GrantFiled: December 14, 2022Date of Patent: November 26, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Weijun Wan, Yue Sheng
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Patent number: 12148489Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.Type: GrantFiled: July 26, 2022Date of Patent: November 19, 2024Assignee: SanDisk Technologies LLCInventors: Yi Song, Sarath Puthenthermadam, Jiahui Yuan