Patents Examined by Fernando Hidalgo
  • Patent number: 11515333
    Abstract: Disclosed are: a three-dimensional flash memory in which the degree of integration in a horizontal direction is improved so as to promote integration; and a manufacturing method therefor. A three-dimensional flash memory according to one embodiment comprises: at least one channel layer extending in one direction; at least one ferroelectric film used as a data storage place while being extended in the one direction so as to encompass the at least one channel layer; and a plurality of electrode layers stacked so as to be vertically connected to the at least one ferroelectric film.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: November 29, 2022
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Yun Heub Song, Chang Wan Choi, Jae Kyeong Jeong
  • Patent number: 11507642
    Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 22, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Vipin Tiwari, Mark Reiten, Nhan Do
  • Patent number: 11501816
    Abstract: Methods, systems, and devices for low voltage ferroelectric memory cell sensing are described. As part of an access operation for a memory cell, gates of two cascodes may be biased to compensate for associated threshold voltages. An extracted signal corresponding to a charge stored in the memory cell may be transferred through a first cascode to charge a first capacitor. Similarly, a reference signal developed at a dummy digit line may be transferred through a second cascode to charge a second capacitor. By comparing the reference signal developed at the dummy digit line to the extracted signal from the memory cell, the effect of variations in memory cell performance on the sense window may be reduced. Additionally, based on biasing the gates of the cascodes, the difference between the signals compared at the sense component may be low compared to other sensing schemes.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11501809
    Abstract: Various implementations described herein refer to a device having an address bus that provides multi-port addresses from multiple ports including a first address from a first port and a second address from a second port. The device may have column contention-detection circuitry that receives the multi-port addresses from the address bus, compares the first address from the first port with the second address from the second port and provides a contention adjustment signal based on the comparison between the first address and the second address. The device may have bitline collision circuitry that receives the contention adjustment signal, senses wire-to-wire variation related to bitline coupling effects and provides a bitline collision signal based on sensing the bitline coupling effects.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: November 15, 2022
    Assignee: Arm Limited
    Inventors: Sanjay Mangal, Bikas Maiti
  • Patent number: 11500026
    Abstract: The invention is directed toward a primary AA alkaline battery. The primary AA alkaline battery includes an anode; a cathode; an electrolyte; and a separator between the anode and the cathode. The anode includes an electrochemically active anode material. The cathode includes an electrochemically active cathode material. The electrolyte includes a hydroxide. The primary AA alkaline battery has an integrated in-cell ionic resistance (Ri) at 22° C. of less than about 39 m?.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 15, 2022
    Assignee: DURACELL U.S. OPERATIONS, INC.
    Inventors: Michael Pozin, Brianna Rose Derooy, Nikolai N. Issaev
  • Patent number: 11502189
    Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 15, 2022
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao, Wei-Chih Kao
  • Patent number: 11501810
    Abstract: A modified double magnetic tunnel junction structure is provided which includes an amorphous spin diffusion layer (i.e., an amorphous non-magnetic, spin-conducting metallic layer) sandwiched between a magnetic free layer and a first tunnel barrier layer; the first tunnel barrier layer contacts a first magnetic reference layer. A second tunnel barrier layer is located on the magnetic free layer and a second magnetic reference layer is located on the second tunnel barrier layer. Such a modified double magnetic tunnel junction structure exhibits efficient switching (at a low current) and speedy readout (high tunnel magnetoresistance).
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: November 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Daniel Worledge, Guohan Hu
  • Patent number: 11495285
    Abstract: Apparatuses and methods for signal line buffer timing control are disclosed. An example apparatus includes a plurality of signal lines including first and second control lines and further including data lines, and further includes first and second signal line buffers. The first signal line buffer includes first driver circuits configured to drive respective data signals on the data lines and to drive first and second control signals on the first and second control lines, respectively. The second signal line buffer includes second driver circuits configured to be activated to receive the data signals. The first and second control signals arrive at the second signal line buffer at different times. The second driver circuits are activated responsive a later one of active first and second control signals and are deactivated responsive to an earlier one of inactive first and second control signals.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Keisuke Fujishiro, Yoshifumi Mochida
  • Patent number: 11494330
    Abstract: A computer platform is disclosed. The computer platform comprises a non-volatile memory to store fuse override data; and a system on chip (SOC), coupled to the non-volatile memory, including a fuse memory to store fuse data and security micro-controller to receive the fuse override data and perform a fuse override to overwrite the fuse data stored in the fuse memory with the fuse override data.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Bharat Pillilli, Saravana Priya Ramanathan, Reshma Lal
  • Patent number: 11488675
    Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: November 1, 2022
    Assignee: Kioxia Corporation
    Inventor: Tetsuaki Utsumi
  • Patent number: 11482272
    Abstract: An electronic device and a semiconductor package structure are provided. The device includes a plurality of semiconductor dies stacked vertically over each other and a power supply system. The semiconductor dies are stacked over the power supply system. The power supply system includes: a voltage generating circuit configured to generate at least one voltage. The at least one voltage is provided to the plurality of semiconductor dies through a power interconnecting structure. The semiconductor package structure includes a package substrate; at least one semiconductor die disposed on the package substrate; and the power supply system disposed on the package substrate. The at least one semiconductor die may include a plurality of semiconductor dies vertically stacked on the package substrate.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: October 25, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Shu-Liang Ning
  • Patent number: 11482264
    Abstract: The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 25, 2022
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Maha Kooli, Roman Gauchi, Pascal Vivet
  • Patent number: 11475932
    Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: October 18, 2022
    Assignee: Sony Group Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 11475927
    Abstract: The present disclosure relates to a static random-access memory and an electronic device. The memory includes at least one storage circuit, wherein the storage circuit includes a first inverter, a second inverter, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a word-line, a first bit-line, a second bit-line, a shift-input line, and a shift-output line. The circuit is used to access data by using the first bit-line and/or the second bit-line when it works in a first mode, and the circuit is used to shift the input data to the shift-input line and output the shifted data through the shift-output line when it works in a second mode. By implementing shift-input and shift-output within the memory, the disclosed embodiment can achieve high-concurrency data access and data update, and it also enables high integration and low power consumption.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 18, 2022
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Xueqing Li, Yiming Chen, Xiaoyang Ma, Mufeng Zhou, Yushen Fu, Yongpan Liu, Huazhong Yang
  • Patent number: 11475955
    Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: October 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junha Lee, Seonkyoo Lee, Jeongdon Ihm, Byunghoon Jeong
  • Patent number: 11468955
    Abstract: An arrangement is described used to throttle data in a connected computer device having a device configured to transmit and receive data from a host, the device comprising, a device controller configured to interact with at least memory array and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: October 11, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11462279
    Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memory states attempts to minimize the use of memory states that are susceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory states on the lower and upper states within the voltage threshold range of the memory device. The distribution of memory states can be modified though the use of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device states that are configured to reduce exposure to negative effects thus prolonging the overall lifespan of the storage device.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: October 4, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amiya Banerjee, Vinayak Bhat, Harish R. Singidi
  • Patent number: 11430503
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: August 30, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Homare Sato
  • Patent number: 11430513
    Abstract: A low voltage forming NVM structure including a plurality of ReRAM devices arranged in a cross bar array and sandwiched between a plurality of first electrically conductive structures and a plurality of second electrically conductive structures. Each first electrically conductive structure is oriented perpendicular to each second electrically conductive structure. The plurality of second electrically conductive structures includes a first set of second electrically conductive structures having a first top trench area A1, and a second set of second electrically conductive structures having a second top trench area A2 that is greater than A1. Each second electrically conductive structure of the first set contacts a surface of at least one of the first electrically conductive structures, and each second electrically conductive structure of the second set contacts a top electrode of at least one of the ReRAM devices.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 30, 2022
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Youngseok Kim, Dexin Kong, Takashi Ando, Hiroyuki Miyazoe
  • Patent number: 11423978
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao