Patents Examined by Fernando Hidalgo
  • Patent number: 12388065
    Abstract: A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: August 12, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Ching Liu, Yih Wang, Chia-En Huang
  • Patent number: 12380940
    Abstract: A semiconductor device includes: a power down control circuit receiving a power down command signal and a chip selection signal, and generating a power down enable signal and a power down exit signal, here, a logic level of the power down enable signal is converted at a first edge of the power down command signal during a power down stage, and a logic level of the power down exit signal is converted at a second edge of the chip selection signal during a power down exit stage; a power control circuit stopping providing a power voltage according to the power down enable signal during the power down stage, and providing the power voltage according to the power down exit signal during the power down exit stage; and an input buffer circuit transmitting signals during the power down exit stage in response to the power down exit signal.
    Type: Grant
    Filed: August 12, 2023
    Date of Patent: August 5, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yupeng Fan
  • Patent number: 12380946
    Abstract: A method of performing an in-memory computation includes storing a first subset of data in a first segment of a first memory array and a second subset of the data in a second segment of the first memory array, latching a first data bit from a first column of memory cells in the first segment of the first memory array, sequentially reading a plurality of second data bits from a second column of memory cells in the second segment of the first memory array, and performing a logic operation on each combination of the latched first data bit and each second data bit.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: August 5, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 12374392
    Abstract: The disclosed 3D IC includes a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit.
    Type: Grant
    Filed: October 6, 2023
    Date of Patent: July 29, 2025
    Assignees: IMEC VZW, Katholieke Universiteit Leuven
    Inventors: Francky Catthoor, Dawit Burusie Abdi
  • Patent number: 12374384
    Abstract: A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock processing circuit, configured to perform two-stage sampling and logical operation on the to-be-processed chip select signal according to a first clock signal to obtain a chip select clock signal; a chip select control circuit, configured to perform sampling on the to-be-processed chip select signal according to the first clock signal to obtain an intermediate chip select signal, and perform logical operations on the intermediate chip select signal, the to-be-processed chip select signal and the to-be-processed command signal to obtain a command decoding signal; and an output sampling circuit, configured to perform sampling on the command decoding signal according to the chip select clock signal to obtain a target command signal.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: July 29, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zequn Huang
  • Patent number: 12374410
    Abstract: Disclosed is a semiconductor device including a plurality of strings connected between a plurality of bit lines and a source line, a plurality of page buffers connected to the plurality of bit lines, respectively, and configured to adjust a voltage level of each of the plurality of bit lines, and a control circuit configured to control the plurality of page buffers to fix a voltage level of a bit line connected to a string including a memory cell on which a program operation has been completely performed and to change a voltage level of a bit line connected to a string including a memory cell on which the program operation has not been completely performed, during a de-trap operation.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: July 29, 2025
    Assignee: SK hynix Inc.
    Inventor: Yeong Jo Mun
  • Patent number: 12367133
    Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: July 22, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Osamu Nagashima, Yoshinori Matsui, Keun Soo Song, Hiroki Takahashi, Shunichi Saito
  • Patent number: 12369497
    Abstract: A magnetoresistive random access memory device includes a bottom electrode, a spin orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) and a top electrode. The bottom electrode includes a first layer and a second layer connected with the first layer. A material of the first layer includes Tax1Ny1, a material of the second layer includes Tax2Ny2, and the following relationships are satisfied: y2/x2>1, y1/x1?1, and y2/x2>y1/x1. The SOT layer is disposed on the bottom electrode. The MTJ is disposed on the SOT layer. The top electrode is disposed on the MTJ.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: July 22, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Hui-Lin Wang
  • Patent number: 12367160
    Abstract: Embodiments of the disclosed technology relate to the operation of devices including memory devices, and more particularly to valid window maximization in a toggle mode (TM) or Open NAND Flash Interface (ONFI) link using systematic skew while compensating for simultaneous switching outputs (SSO) and cross talk.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: July 22, 2025
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shiv Harit Mathur, Niravkumar Natwarbhai Patel
  • Patent number: 12367924
    Abstract: A memory cell includes first through fifth gate structures that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.
    Type: Grant
    Filed: June 14, 2024
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chuan Yang, Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang
  • Patent number: 12367931
    Abstract: Technology is disclosed herein for memory device with control circuitry having an efficient floorplan. Control circuitry resides in a control semiconductor die that is bonded to a memory die NAND strings extending in a z-direction. The memory die has bit lines extending across the NAND strings in an x-direction. First column control circuitry is connected to and configured to control a first set of bit lines. Second column control circuitry is connected to and configured to control a second set of bit lines. The second column control circuitry is stacked in an x-direction with the first column control circuitry. The control die also has system control circuitry configured to control the first column control circuitry and the second column control circuitry. The system control circuitry resides in the floorplan beside the stacked column control circuitry to allow for additional routing of electrical connections above the system control circuitry.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: July 22, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventor: Yuki Mizutani
  • Patent number: 12353731
    Abstract: Provided are a memory controller searching for a data input/output voltage, a memory system, and an operating method of the memory system. The operating method of the memory system configured to search for the data input/output voltage may include searching, by the memory system, for a first driving voltage lower than a first reference voltage by performing first training based on a booting voltage, searching, by the memory system, for a second driving voltage lower than a second reference voltage by performing second training based on the first driving voltage, and setting, by the memory system, the data input/output voltage lower than the first driving voltage, based on the second driving voltage.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: July 8, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byungwook So
  • Patent number: 12346188
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: July 1, 2025
    Assignee: Rambus Inc.
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
  • Patent number: 12341523
    Abstract: Provided is a delay control circuit that can prevent an N-value detection sequence performed by the delay control circuit from exceeding a specific period. The delay control circuit includes: a DLL control circuit that sets a delay amount; a delay line circuit that performs a delay operation; and an N-value detection circuit that receives an input clock signal and an output clock signal and is configured to perform a pre-N-value detection operation. The pre-N-value detection operation includes detecting the number of delayed clock cycles from the input clock signal to the output clock signal as the number of pre-delayed clock cycles before a delay operation is performed. In response to that the number of pre-delayed clock cycles is not greater than a specific value, the DLL control circuit changes the delay amount so that the delay line circuit performs the delay operation in a fast mode.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: June 24, 2025
    Assignee: Winbond Electronics Corp.
    Inventor: Shinya Okuno
  • Patent number: 12334178
    Abstract: A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first and second word line. The first inverter is coupled to the first and third transistor. The second inverter is coupled to the first inverter and the first and third transistor. The first word line is configured to supply a first word line signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first and third transistor. The second word line is configured to supply a second word line signal, and is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and is coupled to the second and fourth transistor. At least the first, second, third or fourth transistor are on the front-side of the substrate.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: June 17, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen Lin Chung, Kao-Cheng Lin, Wei Min Chan, Yen-Huei Chen
  • Patent number: 12334177
    Abstract: A semiconductor memory device includes first and second chips. The first chip includes a first region and a second region. The first region includes memory cells, bit lines, word lines, and first bonding electrodes electrically connected to bit lines. The second region includes contacts electrically connected to word lines and second bonding electrodes electrically connected to contacts. The first bonding electrodes include a third bonding electrode and a fourth bonding electrode adjacent. The second bonding electrodes include a fifth bonding electrode and a sixth bonding electrode adjacent. A distance from a center position of the third bonding electrode to a center position of the fourth bonding electrode and a distance from a center position of the fifth bonding electrode to a center position of the sixth bonding electrode are matched in a range of from 90% to 110%.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: June 17, 2025
    Assignee: Kioxia Corporation
    Inventor: Masayoshi Tagami
  • Patent number: 12327584
    Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.
    Type: Grant
    Filed: June 23, 2023
    Date of Patent: June 10, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donggeon Kim, Bok-Yeon Won, Selyung Yoon, Jonghyuk Kim
  • Patent number: 12315559
    Abstract: A storage circuit includes a multi-stage latch circuit having first to fourth transistor pairs therein, which respectively include a pull-up transistor and a pull-down transistor connected in series through a corresponding one of first to fourth storage nodes. An access circuit is provided, which has a plurality of access transistors of different conductivity type therein. The access transistors are electrically coupled to at least two of the first to fourth storage nodes and configured to enable writing of data bits into at least some of the first to fourth storage nodes, and reading of data bits from at least some of the first to fourth storage nodes. A control circuit is provided, which controls the access circuit during the writing and reading.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: May 27, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kijun Lee, Youngmin Kang, Ikjoon Chang, Kyomin Sohn
  • Patent number: 12300340
    Abstract: A memory system may monitor a bit error rate in data read from a memory in the memory system. The memory system may determine that the monitored bit error rate satisfies an acceptable memory error condition. The memory system may adjust operation of the memory system to decrease the power consumption of the memory system, wherein the adjusted operation results in a new bit error rate monitored from data read from the memory that satisfies the acceptable memory error condition.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: May 13, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ori Laslo, Gilad Kirshenboim
  • Patent number: 12301236
    Abstract: An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: May 13, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daehoon Na, Seonkyoo Lee, Seungjun Bae, Taesung Lee