Abstract: A method of fabricating a device includes forming a multi-layer stack comprising a plurality of electrode layers and a first dielectric layer comprising a non-linear polar material. The method further comprises forming a second dielectric layer on the multi-layer stack, annealing the multi-layer stack, and forming a transistor above a second substrate. A third dielectric layer is formed above the transistor. The second dielectric layer can be bonded with the third dielectric layer and the multi-layer stack can be etched to form a capacitor and a plate electrode connected with the capacitor. An electrode structure can be formed, where at least a portion of the electrode structure extends through the plate electrode and couples with a terminal of the transistor.

Abstract: A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patterns overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction.

Abstract: An apparatus comprising a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line. The apparatus further comprises a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, and wherein the capacitor includes at least four stable states. In at least one example, the capacitor has a first polarization loop and a second polarization loop, wherein the second polarization loop is within the first polarization loop.

Abstract: A semiconductor apparatus, a memory, and an electronic device are disclosed. At least two chips are included. Each of the chips includes: a fuse circuit, configured to generate a first signal and a second signal through fuse burning, and output the first signal and the second signal; an external pad, configured to receive a third signal input to the chip; and a control circuit, connected to the external pad and the fuse circuit. The control circuit is configured to determine, based on the first signal, the second signal, and the third signal, a sequence of executing a command by the chip in which the control circuit is located in the at least two chips.

Abstract: An apparatus that includes a set of memory components of a memory sub-system is disclosed for selectively adjusting a touch up program pulse of an SG. The memory sub-system includes a processing device that detects a condition for performing a select gate (SG) scan for a set of SGs associated with a set of memory components of a memory sub-system. The processing device, in response to detecting the condition for performing the SG scan, accesses data associated with a plurality of memory cells of the set of memory components coupled to an individual SG of the set of SGs. The processing device adjusts a touch up (TU) program pulse based on the accessed data associated with the plurality of memory cells and applies the adjusted TU program pulse to the individual SG to place a threshold voltage (Vt) of the individual SG within a specified operating range.

Abstract: Various 3D cells, array structures, and processes are disclosed. In an embodiment, a 3D cell structure includes a NOR-type memory cell array having rows of memory cells, and each memory cell stores data that controls a cell current for that memory cell. The structure also includes bit lines connected to the rows of memory cells, and each bit line is connected to one memory cell in each of row. The cell structure also includes source lines connected to the rows of memory cells, respectively, and each source line is connected to all the memory cells of a corresponding row of memory cells. The structure is configured so that input signals applied to the bit lines cause cell currents to flow through the memory cells, and in each row of memory cells, selected cell currents combine to form a row cell current that flows on the associated source line.

Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate a divided data strobe signal by dividing the received data strobe signal, and compare the received data strobe signal with the divided data strobe signal to perform a write duty cycle correct operation.

Abstract: A pumping voltage generating circuit can include a control information generating block receiving a pumping enable signal and a refresh sequential signal and generating driving force control information, the driving force control information controlled so that a number of pulses of the refresh sequential signal falling within a target pulse number range is generated during the generation of pulses of the pumping enable signal which have the pumping reference number, a pumping generation block generating a pumping voltage with a total pumping force, the total pumping force depending on the data value of the driving force control information, and a level detection block detecting a level of the pumping voltage and generating the pumping enable signal, the pumping enable signal activated when the level of the pumping voltage is outside a target level range, and deactivated when the level of the pumping voltage falls within the target level range.

Abstract: Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configured to receive the monitored conditions of the stacked memory from the one or more memory monitors, and dynamically adjust operation of the stacked memory based on the monitored conditions. In one or more implementations, a system includes a memory and at least one register configured to store a ranking for each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of the respective portion of the memory. A memory controller is configured to dynamically refresh the portions of the memory at different times based on the ranking for each of the plurality of portions of the memory stored in the at least one register.

Abstract: A semiconductor memory device includes a memory cell array configured to store data, and a control circuit configured to control a write operation of writing data into the memory cell array. In the write operation, the control circuit is configured to receive first data and second data including a parity bit, generate a parity bit for the first data, check whether the parity bit and the parity bit match with each other, and write the first data into the memory cell array.

Abstract: Disclosed are a memory structure, a storage method, an entropy decoding method, a chip, a device, and a storage medium.

Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

Abstract: Various example embodiments provide for handling a power-loss reset (PLRESET) event in a memory system, such as a memory sub-system, with a technique that mitigates the risk of a good block being marked as bad, a memory die being retired prematurely, or both.

Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

Abstract: A method and an apparatus for memory testing are provided. The method includes following steps: after multiple dies are idle for a first time, performing a first stage test on the dies, and setting multiple flags corresponding to the dies that fail the first stage test to a first logic level; after the dies are idle for a second time, performing a second stage test on the dies, and regarding the dies that pass the second stage test and have the corresponding flags set to the first logic level as suspected good dies and keeping the suspected good dies idle; and after the suspected good dies are idle for a third time, performing a third stage test on the suspected good dies.

Abstract: Example memory devices, systems, and methods for reducing verify operation time in memory devices are disclosed. One example method includes performing, based on one of 2N pieces of N-bits data, a first programming operation of the target memory cell to program the target memory cell into an intermediate threshold voltage range P 1 I of a first set of 2N?1 threshold voltage ranges { P 1 0 , P 1 1 , … , P 1 2 N - 2 } , where P 1 2 N - 2 ? and ? P 1 2 N - 3 share a same verify voltage.

Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.

Abstract: Disclosed are a data inversion encoding circuit, an eFLASH memory device and an operation method thereof. The data inversion encoding circuit includes a count and comparison circuit, receiving data with plural bits, counting numbers of 0 and 1 in the bits, and outputting a selection signal when number of 0 is larger than number of 1; an inverter, receiving the data and outputting bit inversion data; and a selection circuit, receiving the data and the bit inversion data, and selecting the data or the bit inversion data based on the selection signal. The bit inversion data is output when number of 0 is larger than number of 1.

Abstract: The present application provides methods of operating memories, memories and memory systems. An example method includes: at a first reading period, performing a sensing operation on memory cells based on a first read voltage, a sensing development duration for the sensing operation performed on the memory cells being not shorter than a first development duration. Based on different sensing development durations, at a first sensing period and a second sensing period of the first reading period, a number of first memory cell, a number of second memory cell and a number of third memory cell are obtained. Based on the number of first memory cell, the number of second memory cell and the number of third memory cell, a valley voltage between a first threshold voltage distribution range and a second threshold voltage distribution range is determined.