Patents Examined by Fernando Hidalgo
  • Patent number: 10811110
    Abstract: Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: October 20, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Wei Zhao, Henry Chin
  • Patent number: 10811097
    Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 20, 2020
    Assignee: SK hynix Inc.
    Inventors: Han Soo Joo, Bong Yeol Park, Ji Hyun Seo, Hee Youl Lee
  • Patent number: 10811101
    Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yafeng Zhang, Liang Qiao, Chunyuan Hou, Jun Xu
  • Patent number: 10803928
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10803912
    Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yadhu Vamshi Vancha, Ali Al-Shamma, Yingchang Chen, Jeffrey Lee, Tz-Yi Liu
  • Patent number: 10803973
    Abstract: A memory management method and a storage controller using the same are provided. The method includes reading a target word-line to identify a plurality of raw Gray code indexes corresponding to a plurality of memory cells of the target word-line; performing a decoding operation on raw data of the target word-line to identify a plurality of decoded Gray code indexes corresponding to the memory cells; calculating a plurality of Gray code absolute bias values corresponding to the memory cells according to the raw Gray code indexes and the decoded Gray code indexes; and identifying one or more abnormal memory cells among the memory cells according to the Gray code absolute bias values; and recording the one or more abnormal memory cells into an abnormal memory cell table, wherein a Gray code absolute bias value of each of the one or more abnormal memory cells is greater than a bias threshold.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 13, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Chia-Wei Chang
  • Patent number: 10796616
    Abstract: An inspection system includes a display device including a nonvolatile memory, an inspection device configured to generate a writing voltage for application to the nonvolatile memory, and a protection part configured to apply the writing voltage to the nonvolatile memory when the writing voltage is within an allowable voltage range, and not to apply the writing voltage to the nonvolatile memory when the writing voltage is not within the allowable voltage range. The application of the writing voltage to the nonvolatile memory enables a multi-time programming (MTP) operation in which reference data writes to the nonvolatile memory.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 6, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Myoung-Ho Kwon
  • Patent number: 10796741
    Abstract: A word line regulator provides a write word line voltage for an asserted word line and includes a write replica circuit, a reference current path, and a regulator circuit. The write replica circuit is a replica of a write path for writing from a low to high resistance value of a resistive memory element of a memory cell. The word line regulator regulates the word line voltage at a value during the write operation of a low to high resistance value such that a select transistor of the memory cell is used as a source follower to regulate a first node of a resistive element of the memory cell being written. The first node is at a higher write voltage than a second node of the resistive element during the write operation, and the first node is located in a write path between the select transistor and the second node.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 6, 2020
    Assignee: NXP USA, Inc.
    Inventors: Jacob T. Williams, Jon Scott Choy, Karthik Ramanan
  • Patent number: 10790007
    Abstract: A memory device and a method of assisting a read operation in the memory device are introduced. The memory device may include a logic circuit, a charge pump, a switch and a sense amplifier. The logic circuit is configured to receive at least one input signal and perform a logic operation on the at least one input signal to output an enable signal. The charge pump is coupled to the logic circuit and is configured to generate a boost voltage according to the enable signal. The switch is coupled between the charge pump and a sensing power supply line, and is configured to control an electrical connection between the charge pump and the sensing power supply line according to the enable signal to supply the boost voltage to the sensing power supply line. The sense amplifier is configured to perform a read operation using the boost voltage from the sensing power supply line.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chi-Shun Lin, Douk-Hyoun Ryu
  • Patent number: 10790022
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. The system can modify a high voltage signal applied to an array of cells during a programming operation as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: September 29, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Patent number: 10790028
    Abstract: An AND type flash memory includes a memory cell array, a plurality of page buffers and a plurality of voltage shifting circuits. The memory cell array is coupled to a plurality of bits lines and source lines. The page buffers are respectively coupled to the bit lines through a plurality of switches, and respectively provides a plurality of control signals. The control signals are transited between a first voltage and a reference voltage. The voltage shifting circuits respectively receive the control signals, generates a plurality of driving signals by shifting voltage values of the control signals, and provides the driving signals to the bit lines. Wherein, the driving signals are transited between a second voltage and the reference voltage, the second voltage is larger than the first voltage.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 29, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Lee-Yin Lin
  • Patent number: 10790000
    Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Kawamura
  • Patent number: 10783945
    Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 22, 2020
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
  • Patent number: 10770157
    Abstract: Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 8, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Wei Zhao, Henry Chin
  • Patent number: 10770150
    Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
  • Patent number: 10770117
    Abstract: A semiconductor storage device includes a source line, a first selection line, word lines, a dummy word line, and a second selection line. A first pillar having a first semiconductor layer extends through the first selection line, the word lines, and the first dummy word line and is connected to the source line. Memory cells are at intersections of the word lines and the first pillar. A conductive layer is on the first semiconductor layer and extends into the first dummy word line. A second pillar with a second semiconductor layer extends through the second selection line and contacts the conductive layer. A bit line is electrically connected to the second semiconductor layer. A control circuit is configured to apply voltages to the various lines during an erasing of the memory cells. A voltage between a source line voltage and a world line voltage is applied to dummy word line.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hideto Takekida
  • Patent number: 10770132
    Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a previous row address to determine whether a read operation is a normal read operation or a burst mode read operation.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 8, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Changho Jung, Keejong Kim, Arun Babu Pallerla, Chulmin Jung
  • Patent number: 10761587
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: September 1, 2020
    Assignee: Rambus Inc.
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
  • Patent number: 10755768
    Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driving arrangement. The distributed write driving arrangement includes: a global write driver including a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line; and a local write driver included at an interior of each segment, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar line.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Patent number: 10741247
    Abstract: A 3D memory array device includes blocks, bit lines, word lines, source lines (SL), complementary metal oxide semiconductors (COMS), and SL sensing amplifiers (SA). Each block includes NAND strings, and each memory cell in the NAND strings stores one or more weights. The bit lines are respectively coupled as signal inputs to string select lines in all blocks. The word lines are respectively coupled to the memory cells, and the word lines in the same layer are as a convolution layer to perform a convolution operation on the inputted signal. Different SL are coupled to all ground select lines in different blocks to independently collect a total current of the NAND strings in each block. The CMOS are disposed under the blocks and coupled to each source line for transferring the total current to each SL SA, and a multiply-accumulate result of each block is outputted via each SL SA.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 11, 2020
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue