Abstract: A peripheral circuit of a memory device is configured to: in the process of programming a first physical page, perform a programming verification to a programming corresponding to the 2(N?M) th memory state; when the program verification of the 2(N?M) th memory state is passed, identifiers corresponding to the 1st to 2(N?M) th memory states stored by the main latch are made different from those corresponding to the 2(N?M)+1st to 2N th memory states; release at least one of the N page latches to cache program data of at least one logical page of the N logical pages of a second physical page; and the programming data of one logical page in the N logical pages of the second physical page is stored in a released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N?2).

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Abstract: An integrated circuit includes a field effect transistor (FET) and a phase change memory (PCM) cell. The PCM cell includes a heater, wherein a bottom surface of the heater is at or below a top surface of the FET.

Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

Abstract: A z-axis compression connector includes a plurality of high-speed signal contacts arranged in a grid of M rows by N columns, and a plurality of signal return contacts arranged between the N columns. A first signal return contact is positioned mid-way in line between a first signal contact and a second signal contact, where the first signal contact is in a first row and a first column and the second signal contact is in the first row and a second column adjacent to the first column.

Abstract: A memory device includes memory cells operably connected to column signal lines and to word signal lines. The column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. The column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level.

Abstract: A semiconductor die includes a first pin configured to output a first on-die termination (ODT) control signal to a second semiconductor die, the second semiconductor die comprising a plurality of second ODT circuits each having an ODT that is responsive to the first ODT control signal; and a second pin configured to receive a second ODT control signal output from the second semiconductor die, the semiconductor die comprising a plurality of first ODT circuits each having an ODT that is responsive to the second ODT control signal.

Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.

Abstract: A semiconductor storage device includes: a storage element that holds data; a bit line that is coupled to the storage element and in which step-down to reference voltage causes data held in the storage element to be inverted, a first step-down circuit that steps down bit line voltage to a first predetermined value equal to or below the reference voltage, the bit line voltage being voltage applied to the bit line; and a control circuit that detects a first voltage change based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter, and that controls a step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected first voltage change.

Abstract: A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.

Abstract: Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.

Abstract: Embodiments of the present disclosure provide a circuit for receiving data, a system for receiving data, and a memory device. The circuit for receiving data includes: a first amplification module, including: an amplification unit, provided with a first node, a second node, a third node, and a fourth node; a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor being provided with one terminal connected to the first node and another terminal connected to one terminal of the second NMOS transistor, another terminal of the second NMOS transistor being connected to the second node, a gate of one of the first NMOS transistor and the second NMOS transistor being configured to receive a first complementary feedback signal, and a gate of the other one of the first NMOS transistor and the second NMOS transistor being configured to receive an enable signal.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

Abstract: Embodiments relate to a sense amplifier circuit and a data read method. The sense amplifier circuit includes: a first P-type transistor connected to a first signal terminal; a second P-type transistor connected to a second signal terminal; a first N-type transistor connected to a third signal terminal; a second N-type transistor connected to a fourth signal terminal; a first offset cancellation subcircuit configured to connect a first read bit line to a second complementary read bit line in response to a first offset cancellation signal; a second offset cancellation subcircuit configured to connect a first complementary read bit line to a second read bit line in response to a second offset cancellation signal; a first write-back subcircuit configured to connect the first complementary read bit line to the second complementary read bit line in response to a first write-back signal; and a second write-back subcircuit.

Abstract: The present disclosure provide latch performance detecting method and a device. The method includes: extracting circuit structure information of a latch, having a transmission gate and a latch unit, an output terminal of the transmission gate is coupled to the input terminal of the latch unit, and the input terminal is coupled to the output terminal of the drive unit corresponding to the latch; the resistance value of the equivalent resistor of the latch is determined based on the circuit structure information, The first terminal of the equivalent resistor is the output terminal of the driving unit, and the second terminal is the input terminal of the latching unit; based on the resistance value of the equivalent resistor, the latching performance is determined. The embodiments of the present disclosure can accurately detect whether the latch is in a metastable state, which helps to improve the performance of the circuit.

Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

Abstract: A memory device includes a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output, based on repair information stored therein, a repair use signal corresponding to an input address; and an error correction circuit configured to: receive the second data as a first error correction code from the second cell block while selectively receiving, according to the repair use signal, the third data as a second error correction code from the third cell block, and correct errors in the first data from the first cell blocks using the first and second error correction codes.