Patents Examined by Fernando Hidalgo
  • Patent number: 10950790
    Abstract: A two-terminal memory device and methods for its use are provided. In the device, a bottom electrode is electrically continuous with a first operating terminal, and a control gate electrode is electrically continuous with a second operating terminal. A stack of insulator layers comprising a hopping conduction layer and a tunnel layer is contactingly interposed between the bottom electrode and the control gate electrode. The tunnel layer is thinner than the hopping conduction layer, and it has a wider bandgap than the hopping conduction layer. The hopping conduction layer consists of a material that supports electron hopping transport.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: March 16, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Matthew Marinella, Sapan Agarwal
  • Patent number: 10949745
    Abstract: A cognitive learning device includes inputs with each including an input path having a transistor device having a storage capacity. A circuit is responsive to the inputs and selects an input set in accordance with a current task, wherein the input set selected modifies a characteristic of the transistor device of one or more corresponding input paths to bias the input set for selection for subsequent accesses.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10942873
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Patent number: 10943667
    Abstract: A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi, Wei-Chang Zhao
  • Patent number: 10943661
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: March 9, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Patent number: 10937513
    Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Mi Ko, Kwang Ho Baek, Ji Hwan Kim, Seong Je Park, Sung Hoon Ahn, Young Don Jung
  • Patent number: 10938395
    Abstract: An electronic device including: a delay circuit configured to adjust a delay of an input for generating an output signal; and an input selection circuit coupled to the delay circuit, the input selection circuit configured to control a phase for a clock input based at least in part on a measurement of a delay corresponding to the delay circuit in generating the input.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dan Shi, Tyler J. Gomm, Michael J. Allen
  • Patent number: 10930353
    Abstract: Provided are a non-volatile memory device and an operating method thereof. The non-volatile memory device includes a memory cell array having a vertically stacked structure, a bit line for applying a programming voltage to the memory cell array, and a control logic. The memory cell array includes memory cells that each include a corresponding portion of a semiconductor layer and a corresponding portion of a resistance layer. The memory cells include a non-selected memory cell, a compensation memory cell, and a selected memory cell. The control logic is configured to apply an adjusted program voltage to the selected memory cell, based on applying a first voltage to the compensation memory cell, a second voltage to the selected memory cell, and a third voltage to the non-selected memory cell. The adjusted program voltage may be dropped compared to the programming voltage due to the compensation memory cell.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungho Yoon, Seyun Kim, Jinhong Kim, Soichiro Mizusaki, Youngjin Cho
  • Patent number: 10923184
    Abstract: An SRAM device has a voltage input terminal configured to receive a first signal at a first voltage level. A level shifter is connected to the voltage input terminal to receive the first signal, and the level shifter is configured to output a second signal at a second voltage level higher than the first voltage level. A memory cell has a word line and a bit line. The word line is connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level, and the bit line is connected to the voltage input terminal to selectively receive the first signal at the first voltage level. A sense amplifier is connected to the bit line and is configured to provide an output of the memory cell. The sense amplifier has a sense amplifier input connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: February 16, 2021
    Inventors: Sanjeev Kumar Jain, Atul Katoch
  • Patent number: 10916277
    Abstract: A memory device includes a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information; a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device; a peripheral circuit performing a read operation on the storage block; and a control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 10916292
    Abstract: A method for performing a refresh operation based on system characteristics is provided. The method includes determining that a current operating condition of a memory component is in a first state. The method also includes detecting a change in the operating condition from the first state to a second state. The method further includes setting a refresh period associated with the memory component based on the change of the operating condition. The refresh period corresponds to a period of time between a first time when a write operation is performed on a segment of the memory component and a second time when a refresh operation is to be performed on the segment. Moreover, the method includes performing the refresh operation according to the refresh period.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: February 9, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Zhenming Zhou, Tingjun Xie
  • Patent number: 10878934
    Abstract: A memory device and an electronic device are provided. Different embodiments of local redundancy decoder circuits that can be used in the memory device and the electronic device are disclosed.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 29, 2020
    Inventors: Chien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hau-Tai Shieh
  • Patent number: 10878855
    Abstract: A charge sharing type lower-cell-voltage (LCV) write assist takes advantage of unused metal layers on top of a memory array to implement capacitance without incurring area costs. Only one-time fixed amount expenses of charge are needed for a given LCV level during the charge sharing phase of each write operation. Metal wires parallel to the bit cell power wires have good capacitance matching for charge sharing among all memory density configurations, thus benefitting memory compiler design.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 29, 2020
    Inventors: Yangsyu Lin, Chiting Cheng, Wei-jer Hsieh
  • Patent number: 10879266
    Abstract: A semiconductor device includes a substrate including a doped region of a first doping concentration that extends downward from an upper surface of the substrate; a first stack on the upper surface, including first insulating layers and first conductive layers alternatively stacked, a first channel layer, a first memory layer and a first conductive connector configured to receive a first voltage, the first conductive connector on the first channel layer, having a second doping concentration; a second stack on the first stack including second insulating layers and second conductive layers alternatively stacked, a second channel layer, a second memory layer, the second conductive layer configured to receive the second voltage; a second conductive connector on the second channel layer, configured to receive an erasing voltage, the first conductive connector electrically connected to the first and second channel layers; the first doping concentration smaller than the second doping concentration.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: December 29, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Guan-Wei Wu, Yao-Wen Chang, I-Chen Yang
  • Patent number: 10878868
    Abstract: A nonvolatile memory device includes: a plurality of word lines that are stacked; a vertical channel region suitable for forming a cell string along with the word lines; and a voltage supplier suitable for supplying a plurality of biases required for a program operation on the word lines, where a negative bias is applied to neighboring word lines disposed adjacent to a selected word line at an end of a pulsing section of a program voltage which is applied to the selected word line.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Jin Yong Oh
  • Patent number: 10872661
    Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 22, 2020
    Assignee: Microchip Technology Inc.
    Inventors: Fengliang Xue, Fethi Dhaoui, Victor Nguyen, John L. McCollum
  • Patent number: 10872656
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: writing a first data and a second data to a first physical erasing unit; copying the first data from the first physical erasing unit to a second physical erasing unit; and copying the second data from the first physical erasing unit to a third physical erasing unit, wherein the memory sub-module to which the second physical erasing unit belongs is different from the memory sub-module to which the third physical erasing unit belongs.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10872673
    Abstract: A semiconductor memory cell includes a memory cell, a word line and a source line both connected to the memory cell, and a control circuit. During a read operation on the memory cell, the control circuit applies a first voltage to the word line, applies a second voltage greater than the first voltage to the word line, and then applies a third voltage which is greater than the first voltage and smaller than the second voltage to the word line. During the read operation on the memory cell, the control circuit also applies a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and then applies a fifth voltage smaller than the fourth voltage to the source line.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Toshifumi Watanabe, Naofumi Abiko, Mario Sako
  • Patent number: 10867655
    Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan D. Harms, David Hulton, Jeremy Chritz
  • Patent number: 10868158
    Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: December 15, 2020
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao, Wei-Chih Kao