Patents Examined by Fernando Hidalgo
  • Patent number: 10734061
    Abstract: In accordance with one embodiment, a computer-implemented method is provided, comprising: configuring code to cause at least part of hardware to operate as a double data rate (DDR) memory controller and to produce one or more capture clocks, where: a timing of at least one of the one or more capture clocks is based on a first clock signal of a first clock, the first clock signal is a core clock signal or a signal derived from at least the core clock signal, the at least one of the one or more capture clocks is used to time a read data path, the at least one of the one or more capture clocks is used to capture read data into a clock domain related to a second clock, the first clock and the second clock being related in timing such that at least one of: the second clock is derived from the first clock, or the first clock is derived from the second clock; and providing access to the code.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 4, 2020
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10734054
    Abstract: A magnetic structure includes a magnetic tunnel junction based on a synthetic antiferromagnetic free layer which is regulated by an electric field, and a spin-orbit layer located below the magnetic tunnel junction. The transformation from the antiferromagnetic coupling to the ferromagnetic coupling of the free layer based on a synthetic antiferromagnetic multilayer structure is controlled by an electric field. A spin-orbit torque magnetic random access memory, which includes the magnetic structure, is able to realize stable data writing under the combined interaction of electric field and current, and has advantages of simple structure for scaling, ultralow power consumption, ultrahigh speed of switching, radiation resistance and non-volatility.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: August 4, 2020
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Tai Min, Xue Zhou, Xuesong Zhou, Lei Wang
  • Patent number: 10726898
    Abstract: A sense amplifier circuit for sensing a data state of a data cell during a read cycle is described. The circuit includes a first stage with first circuitry to output a reference voltage and a data voltage relating to the data state of the data cell. The circuit further includes a second stage with circuitry to amplify a difference between the reference voltage and the data voltage. This circuitry includes a plurality of inverters and a plurality of capacitors. The read cycle includes a compensation phase. During the compensation phase the circuitry stores, at the capacitors, a voltage difference caused by a device mismatch of the inverters. After the compensation phase the circuitry amplifies the difference between the reference voltage and the data voltage, and compensates for the device mismatch using the stored voltage difference at the capacitors.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas Martin Maffitt, John Kenneth Debrose
  • Patent number: 10714201
    Abstract: A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 14, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Chieh-Tse Lee, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 10714161
    Abstract: A semiconductor device includes: a memory region selection circuit for generating memory region select signals based on a memory region address signal and a mode identification signal, and activating one or more memory region select signals among memory region select signals during a first mode, or activating two or more memory region select signals among the memory region select signals during a second mode; a column selection circuit for generating column select signals based on a column address signal and the mode identification signal, and changing the column select signals during the first mode, or retaining the column select signals during the second mode; and memory regions of which one or more memory regions are accessed during the first mode or two or more memory regions are accessed during the second mode, based on the memory region select signals and the column select signals.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Tae-Yong Lee
  • Patent number: 10699768
    Abstract: Apparatuses and methods for a command decoder delay are disclosed. An example apparatus includes a command decoder which may receive memory access command. The command decoder may provide an output command based on the memory access command to a command path at a first time. The command decoder may also provide the output command to a data path at a second time, wherein the second time is delayed relative to the first time.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Vijayakrishna J. Vankayala, Jason M. Brown
  • Patent number: 10692582
    Abstract: A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Ryun Kim
  • Patent number: 10685720
    Abstract: According to one embodiment, a non-volatile first memory includes a plurality of first storage areas. A second memory stores a plurality of first addresses each is address information of a second storage area. The second storage area is a first storage area in a first state. A third memory stores a counted value for the second storage area. A determiner circuit reads, at a time of a read access to the first memory, at least one of the first addresses and compares the read second address with a third address to determine whether a third storage area is in the first state. The third address indicates a location of the third storage area. The third storage area is a first storage area to be read. An update circuit increments, for the third storage area, the counted value, when the third storage area is in the first state.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoto Oshiyama
  • Patent number: 10679688
    Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Titash Rakshit, Borna J. Obradovic, Ryan M. Hatcher, Jorge A. Kittl
  • Patent number: 10679692
    Abstract: A memory apparatus and a majority detector thereof are provided. The majority detector includes a pull-up circuit, a first switch, a second switch, a plurality of first transistors, a plurality of second transistors and a sense amplifying circuit. The pull-up circuit provides a first voltage to a first node and a second node according to a control signal before a sensing period. The first switch and the second switch provide a second voltage to the first node and the second node respectively according to the control signal during the sensing period. Control ends of the first transistors each receives one of a plurality of values of a data signal. Control ends of the second transistors each receives an inverse value of the one of the values of the data signal. The sense amplifying circuit generates a sensing result according to a voltage difference between the first node and the second node during the sensing period, and the sensing result indicates a majority value among the values.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 9, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Yuji Nakaoka
  • Patent number: 10665607
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano, Akio Nishida
  • Patent number: 10665291
    Abstract: A memory device includes: a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines; a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10658062
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10656605
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating a target sequence from a source sequence. In one aspect, the system includes a recurrent neural network configured to, at each time step, receive am input for the time step and process the input to generate a progress score and a set of output scores; and a subsystem configured to, at each time step, generate the recurrent neural network input and provide the input to the recurrent neural network; determine, from the progress score, whether or not to emit a new output at the time step; and, in response to determining to emit a new output, select an output using the output scores and emit the selected output as the output at a next position in the output order.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 19, 2020
    Assignee: Google LLC
    Inventors: Chung-Cheng Chiu, Navdeep Jaitly, Ilya Sutskever, Yuping Luo
  • Patent number: 10651300
    Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 12, 2020
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao, Wei-Chih Kao
  • Patent number: 10650893
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: May 12, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Patent number: 10643681
    Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic (SyAF) layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, SyAF layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the SyAF layers to grow in the FCC (111) direction.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 5, 2020
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
  • Patent number: 10643119
    Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Pi-Feng Chiu, Won Ho Choi, Wen Ma, Martin Lueker-Boden
  • Patent number: 10636510
    Abstract: A semiconductor device includes a fuse array circuit including a plurality of fuse cell arrays, and configured to output fuse data based on one or more fuses that have been ruptured or not within a fuse cell array; and a fuse control circuit configured to compare the fuse data and one or more failure addresses, and re-perform a rupture operation for the fuse cell array when the fuse data and the failure addresses indicate a difference between the fuse data and the failure addresses.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Joohyeon Lee
  • Patent number: 10629252
    Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo