Abstract: An array of light emitting diodes (LED) are laid out as a dot matrix array as a display panel. Each LED is accessed by two dimensional addressing from a first set of parallel horizontal interconnections and a second set of orthogonal interconnections. The two sets of orthogonal interconnections are printed on two sides of a substrate. One of the two electrodes of an LED, which mounted on the top of the substrate, is fed through the substrate with a via hole and connected to the orthogonal interconnection at the bottom of the substrate. The size of the display panel is configurable by removing certain rows and/or columns. More than one partitioned blocks can be pieced together by aligning and coupling the corresponding orthogonal interconnections through a motherboard.

Abstract: A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.

Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.

Abstract: An organic EL display device including a first TFT (30) for switching operation, a second TFT (40) for driving an organic EL element, and an organic EL element (60) having an anode (61), a cathode (66), and a light emissive element layer (65) sandwiched between these electrodes. The first TFT (30) has an n-channel and an LDD structure, exhibiting a high-speed response and superior retaining characteristics. The second TFT (40) has a p-channel, and therefore exhibits superior current controllability. By combining these two types of TFTs to drive the organic EL element for each pixel, a high ON current can be achieved with a reduced leakage current, thereby producing a quality gradation display.

Abstract: An array of semiconductor circuit elements such as light-emitting elements includes a semiconductor layer partially covered by a dielectric film. A first interconnecting pad such as a wire-bonding pad is electrically coupled by conductive paths passing through the semiconductor layer to electrodes of a first group of semiconductor circuit elements formed in the semiconductor layer. A second interconnecting pad such as a wire-bonding pad, formed on the dielectric film, is electrically coupled to electrodes of a second group of semiconductor circuit elements formed in the semiconductor layer by conductive paths insulated from the semiconductor layer by the dielectric film. The second conductive paths cross the first conductive paths at points at which the first conductive paths pass through the semiconductor layer, so that only a single layer of metal interconnecting lines is needed.

Abstract: A matrix converter for transforming electrical energy between at least one voltage source, in particular a power supply network, and at least one current source, in particular a load, said converter including a matrix of switches connecting said voltage sources to said current sources, wherein each of said switches has two terminals disposed in respective distinct parallel planes and a photoconductive diamond substrate interposed between said two terminals of the switch, each switch being controlled by means of a light source irradiating the diamond substrate interposed between the two terminals.

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Abstract: A semiconductor structure (and method for forming) having transistors having both metal gates and polysilicon gates on a single substrate in a single process is disclosed. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. The method patterns the metal seed layer to leave metal seed material in metal gate seed areas above the substrate. Next, the method patterns a polysilicon layer into polysilicon structures above the substrate. Some of the polysilicon structures comprise sacrificial polysilicon structures on the metal gate seed areas and the remaining ones of the polysilicon structures comprise the polysilicon gates. The patterning of the polysilicon gates forms the sacrificial gates above all the metal gate seed areas. Following that, the invention forms sidewall spacers, and source and drain regions adjacent the polysilicon structures.

Abstract: By adding a novel improvement to the technique disclosed in JP 8-78329 A, a manufacturing method in which film characteristics of a semiconductor film having a crystalline structure are improved is provided. In addition, a TFT having superior TFT characteristics, such as field effect mobility, which uses the semiconductor film as an active layer, and a method of manufacturing the TFT, are also provided. A metallic element which promotes the crystallization of silicon is added to a semiconductor film having an amorphous structure and an oxygen concentration within the film of less than 5×1018/cm3. The semiconductor film having an amorphous structure is then heat-treated, forming a semiconductor film having a crystalline structure. Subsequently, an oxide film on the surface is removed. Oxygen is introduced to the semiconductor film having a crystalline structure, and processing is performed such that the concentration of oxygen within the film is from 5×1018/cm3 to 1×1021/cm3.

Abstract: In a metal oxide semiconductor (MOS) field effect transistor configuration, a source, a drain and a gate are embedded between a semiconductor pillar that extends away from a semiconductor body and forms a body region. A filling insulator surrounds the semiconductor pillar and is situated on the semiconductor body for insulating the MOSFET.

Abstract: A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are connected electrically to bonding pads on the integrated circuit chips in the chip-receiving windows such that internal electrical connection among the integrated circuit chips can be established via the internal connection leads. A plurality of external connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows, and are connected electrically to the bonding pads on the integrated circuit chip in the adjacent chip-receiving window.

Abstract: A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers.

Abstract: Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

Abstract: A structure of a flash memory, having a deep P-well formed in an N-type substrate, an N-well formed in the deep P-well, a stacked gate structure formed on the substrate, an N-type source region and an N-type drain region formed in an N-well at two respective sides of the stacked gate, where the N-type source region is in electric contact with the N-well, a P-well formed in the N-well to encompass the N-type source region and to extend towards the N-type drain region through the portion under the stacked gate, and a contact window formed at the junction of the N-type source region and the P-well to electrically short circuit the N-type source region and the P-well. The flash memory uses F-N tunneling effect for programming and the channel F-N tunneling effect to perform the erase operation.

Abstract: Chemical mechanical polishing (CMP) produces thickness variations over the surface of a chip or die that depends on many factors. The present invention provides for characterization of the thickness variations over the surface area, and accepting these variations in the detailed design of the components that are to be distributed over the entire surface of the die. Any device with parameters that depend on the layer thickness that is subject to CMP will have variations in those parameters depending upon where the device is located on the die. The present invention characterizes the thickness variations and modifies the physical design of other mechanical aspects of the device so as to compensate for the thickness variations. The result is devices that have acceptable parameters regardless of their location on the chip.

Abstract: A method and system for performing failure analysis on a silicon on insulator (SOI) semiconductor device is disclosed. The SOI device includes a plurality of conductive structures in a silicon region. The silicon resides on a box insulator, which resides on a silicon substrate. The method and system include providing a cross-section of the SOI semiconductor device. The cross-section of the SOI semiconductor device includes a portion of the plurality of conductive structures. The method and system also include staining the cross-section of the SOI semiconductor device using a stain. The stain etches the silicon region in the SOI semiconductor device without etching a remaining portion of the SOI semiconductor device not composed of silicon.

Abstract: In a semiconductor light-emitting element, a first DBR and a second DBR, with a specified spacing left between them, form a resonator, and a single quantum well active layer is positioned at the loop of a standing wave within this resonator. The single quantum well active layer is composed of a Ga0.5In0.5P well layer and a pair of (Al0.5Ga0.5)0.5In0.5P barrier layers, which sandwiches the Ga0.5In0.5P well layer therebetween. The impurity concentration of the (Al0.5Ga0.5)0.5In0.5P barrier layers is higher than that of the Ga0.5In0.5P well layer. For example, the impurity concentration of the Ga0.5In0.5P well layer is set to 2×1016 cm−3, while the impurity concentration of the (Al0.5Ga0.5)0.5In0.5P barrier layers is set to 2×1018 cm−3.

Abstract: The invention uses the optical nonlinearity of electrically biased exciton polariton in a strong coupling regime or exciton polariton in a strong coupling regime with spatially separated electron and hole pairs. The method comprises providing a signal light (1300) to an exciton polariton system in a strong coupling regime and excitons with spatially separated electron and hole pairs, providing a control light (1302) to the exciton polariton system and removing the control light (1302). Various applications are available, including optical turnstiles, all-optical switches, all-optical phase retardation, low-power saturable transmitters and mirrors. In addition, the applications may operate at single- or few-photon levels.

Abstract: A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.

Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode