Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

Abstract: In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolation trench. A vertical transistor that is used, for example, in a DRAM memory cell and a method for making the transistor includes connecting the channel region of the vertical transistor to the substrate by disposing a conductive layer in the isolation trench between a lower insulation filling and an upper insulation filling.

Abstract: An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

Abstract: A double-side display structure for an organic light emitting diode (OLED) and a method of manufacturing the same includes: plating an organic layer on an OLED element by vaporization; plating an organic protection layer on the organic layer to protect various organic layers from being damaged by electron bombardment during the OLED element subject to ITO sputtering in the later processing; plating an electron injecting layer and a thin metal film of a mating energy level on the organic protection layer; and plating a transparent conductive film on the electron injecting layer and the thin metal film to increase conductivity and protect the thin metal film from corrosion.

Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.

Abstract: An electro-luminescence panel that is adaptive for maximizing a capacitance of a storage capacitor. A plurality of electro-luminescence cells are arranged at crossings between gate lines and data lines in the panel. An electro-luminescence cell driving circuit drives the electro-luminescence cells. In the driving circuit, a power supply supplies power to the electro-luminescence cells. A first thin film transistor is connected between the power supply and the electro-luminescence cell. A second thin film transistor is connected between the data line and a gate electrode of the first thin film transistor to serve a switch of the electro-luminescence cell. A storage capacitor is connected between the gate electrode of the first thin film transistor and a pre-stage gate line. Accordingly, a capacitance value of the storage capacitor is maximized with the aid of the pre-stage gate line upon formation of the storage capacitor, thereby preventing flicker caused by a kickback phenomenon.

Abstract: Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, a first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than a second portion which is located on the data wire, and the photoresist layer is totally removed on other parts. The thin portion is made by controlling the amount of irradiating light or by a reflow process to form a thin portion, and the amount of light is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

Abstract: A solid state image sensor is constructed such that a plurality of linear image sensors are provided to have at least one row of photodiodes in each of the plurality of linear image sensors and a photodiode array is formed by arranging the plurality of linear image sensors side by side. A control gate electrode used to retrieve electric charges and a polysilicon electrode serving as a charge transfer electrode are provided between the pluraliielding conductive film is provided on the polysilicon electrode to partition the plurality of linear image sensors into individual linear image sensors. Accordingly, a light beam incident on a certain linear image sensor can be prevented from entering another linear image sensor adjacent to the certain linear image sensor, thereby reducing a difference between the amounts of signal charges outputted from different linear image sensors and suppressing smear.

Abstract: A spin transistor employing the ferromagnetic semiconductor/semiconductor heterojunction is disclosed. The ferromagnetic semiconductor layers form heterojunctions directly on the source and drain of a regular field effect transistor. Using room temperature ferromagnetic semiconductor materials such as iron doped titanium oxide, the spin transistor can have improved spin injection efficiency due to the conductance matching of the ferromagnetic semiconductor with the semiconductor source and drain. The spin transistor further comprises writing plates to modify the magnetic polarization of the ferromagnetic layers to provide memory states. The spin transistor can be used as a memory cell in a magnetic random access memory with potentially large memory signal by utilizing the magnetic moment induced resistivity change.

Abstract: A novel measurement method is provided capable of measuring characteristics of semiconductor integrated circuit devices without incurring the influence of external measuring means. A prescribed delay time applied to an address supplied from a microprocessor 11 to a memory 12 during normal operation is increased and a critical time where data corresponding to the address can no longer be read in by the microprocessor 11 from the memory 12 via the latch circuit 14 correctly is obtained. The delay time with which the address is supplied to the latch circuit 14 is increased with the address being supplied in a short-circuited manner to the latch circuit 14 rather than being supplied to the memory 12 and a short-circuit critical delay time where the address can no longer be read in correctly is obtained. A time difference corresponding to a difference in critical delay times is then obtained as the memory access time of the semiconductor integrated circuit device 10.

Abstract: A high-speed transparent refresh DRAM-based memory cell and architecture are disclosed. Each memory cell consists of 4 transistors configured to incorporate differential data storage (i.e., storing a true logic state and a complementary logic state), with each pair of transistors having a dual port configuration and forming one of a complementary pair of storage nodes for the memory cell. Each memory cell is coupled to 2 wordlines and 4 digit lines. Since the memory cell stores complementary data, and since a logic LOW state is rewritten to a given memory cell faster than a logic HIGH state is rewritten, the logic LOW state is rewritten and the complementary logic state is known to be a logic HIGH state. As a result, both the logic LOW and logic HIGH states are rewritten to the memory cell faster than independently writing a logic HIGH state.

Abstract: A programmable device including: an antifuse; a resistive heating element having a substantially temperature to power response, the resistive heating element adjacent to but not in contact with the antifuse; and means for passing an electric current through the resistive heating element in order to generate heat to raise the temperature of the antifuse sufficiently high enough to decrease a programming voltage of the antifuse, a time the programming voltage is applied to the antifuse or both the programming voltage of the antifuse and the time the programming voltage is applied to the antifuse.

Abstract: An undoped In0.52Al0.48As buffer layer (thickness: 500 nm), an undoped In0.53Ga0.47As channel layer (thickness: 30 nm), an n-type delta doped layer for shortening the distance between the channel layer and a gate electrode and attaining a desired carrier density, an undoped In0.52Al0.48As Schottky layer, and an n-type In0.53Ga0.47As cap layer doped with Si (thickness: 50 nm) are formed in this order on the principal surface of an Fe-doped InP semi-insulating substrate. An n-type GaAs protective layer doped with Si (thickness: 7.5 nm) is formed between the cap layer and source/drain electrodes for protecting the cap layer.

Abstract: Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include an electrode, an adhesive material, an insulating material between the electrode and the adhesive material, wherein a portion of the adhesive material, a portion of the insulating material, and a portion of the electrode form a substantially planar surface. The phase change memory may further include a phase change material on the substantially planar surface and contacting the electrode, the adhesive material, and the insulating material.

Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

Abstract: There is provided a semiconductor device using a semiconductor thin film having high crystallinity, which is formed by a manufacturing method with high productivity. When active layers of an amorphous silicon film are crystallized, germanium is used as a catalytic element for facilitating crystallization. When a heat treatment is carried out in a state where the active layers are in contact with a germanium film through an opening portion provided in a mask insulating film, the active layers made of a polysilicon film are obtained by crystal growth in a lateral direction.

Abstract: In a semiconductor integrated circuit device having a memory cell which includes a MIS.FET and a capacitance element, the conductivity type of a low-resistance polysilicon film which constitutes the gate electrode (5g) of the memory cell selecting MIS.FET (Q) of n-channel type constituting the memory cell is set at p+-type in order to enhance the refresh characteristics of the memory cell.

Abstract: A semiconductor integrated circuit device comprises vertical power supply wiring 12 divided into first and second narrow-width vertical power supply wirings 12a and 12b, vertical ground wiring 14 disposed in parallel with vertical power supply wiring 12 and divided into first and second narrow-width vertical ground wirings 14a and 14b, auxiliary vertical power supply wiring 22 connecting first narrow-width vertical power supply wiring 12a and second narrow-width vertical power supply wiring 12b, and auxiliary vertical ground wiring 24 connecting first narrow-width vertical ground wiring 14a and second narrow-width vertical ground wiring 14b.

Abstract: A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detector for detecting a transition of the first node from a first to a second state, wherein the transition detector, in response to the transition, disables the transfer gate and enables the reset signal; and 3) a feedback loop circuit for detecting enabling of the reset signal. The feedback loop circuit, in response to the enabling, changes the first node from the second state back to the first state. The transition detector, in response to the changing of the first node back to the first state, disables the reset signal.