Patents Examined by Florin Munteanu
  • Patent number: 4949247
    Abstract: Apparatus for performing vector operations on the data elements of vectors includes a vector processor for performing arithmetic operations on the elements, a vector memory for storing the data elements for use by the processor, the vector memory having a port for reading and writing, and at least one staging register interposed between the vector memory port and the processor; the port and the register are each sufficiently wide to span more than one data element. As a result, on average fewer than one read or write operation per data element is required to access the vector memory via the port. Access to the vector memory port (i.e.
    Type: Grant
    Filed: February 23, 1988
    Date of Patent: August 14, 1990
    Assignee: Stellar Computer, Inc.
    Inventors: R. Ashley Stephenson, Kevin B. Normoyle
  • Patent number: 4914586
    Abstract: A database of interests is maintained in a distributed computing system to register the individual interests of users in centrally stored non-textual media files, such as digital voice, music, scanned-in image, and video files. Uniquely named piece table style persistent data structures are employed to give users controlled access to the underlying non-textual media files by embedded name reference to such piece tables in ordinary messages or text files, so a database of piece tables is also maintained. A garbage collector periodically enumerates the interest database to delete interest entries which have been invalidated. Aged piece tables are deleted from the reference database when there no longer are any recorded interests referring to them, and non-textual media files are deleted to reclaim the storage space allocated to them when there no longer are any piece tables referring to them.
    Type: Grant
    Filed: November 6, 1987
    Date of Patent: April 3, 1990
    Assignee: Xerox Corporation
    Inventors: Daniel C. Swinehart, Douglas B. Terry
  • Patent number: 4914575
    Abstract: An input/output channel apparatus includes a system bus controller for generating a memory read request and outputting a memory address. Generation of the memory read request is inhibited in response to a request inhibit instruction generated by a request-inhibit generating section. When a memory bank other than one accessed in response to the immediately preceding memory read request is accessed, the request-inhibit instruction is generated. The request-inhibit instruction is canceled when memory interleaved data on the basis of the memory read requests for the same memory bank are input to a buffer in the apparatus.
    Type: Grant
    Filed: August 27, 1987
    Date of Patent: April 3, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Kihara, Hiroyuki Kaneko
  • Patent number: 4908790
    Abstract: Backup battery switching circuitry for a microcomputer or a microprocessor includes circuitry for selectively coupling a backup battery to a power supply output terminal of the microcomputer or microprocessor for powering an external circuit such as a static RAM. The backup battery voltage is normally coupled to the power supply output terminal in the absence of a primary power source, but may be isolated from the power supply output terminal when a predetermined voltage is applied to a logic input pin and a predetermined sequence of events is executed by the microcomputer or microprocessor.
    Type: Grant
    Filed: March 10, 1988
    Date of Patent: March 13, 1990
    Assignee: Dallas Semiconductor Corporation
    Inventors: Wendell L. Little, Stephen N. Grider
  • Patent number: 4907193
    Abstract: A word processing apparatus is capable of logotype printing with a standard dot matrix pattern, and is controlled as to provide zero spacing between characters at logotype printing.
    Type: Grant
    Filed: January 24, 1989
    Date of Patent: March 6, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Katsumi Masaki
  • Patent number: 4907187
    Abstract: A data processing apparatus includes a self-running type shift register and this shift register includes a plurality of latch registers arranged in a cascade fashion. The latch register latches a data packet on a word basis. In each latch register, a coincidence element is disposed in association therewith and these coincidence elements allow transfer of data from a post-stage latch register provided that a pre-stage latch register is vacant. A data processing element is installed between two latch registers and the data processing element processes operand data from either or both of the two latch register in response to the kind of processing shown by an operation code comprised in the preceding word. The result of processing is transferred to the pre-stage latch register when the pre-stage latch register is placed in the vacant state under control of the coincidence element.
    Type: Grant
    Filed: May 16, 1986
    Date of Patent: March 6, 1990
    Assignees: Sanyo Electric Co., Ltd., Sharp Kabushiki Kaisha, Matsushita Electric Industrial Co., Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroaki Terada, Katsuhiko Asada, Niroaki Nishikawa, Souichi Miyata, Satoshi Matsumoto, Hajime Asano, Masahisa Shimizu, Hiroki Miura, Kenji Shima
  • Patent number: 4905183
    Abstract: A pattern generator permitting to output patterns at high speed and having an operating function, which is suitable for generating test patterns for memory ICs. Although it was known heretofore to increase the operating speed by operating a plurality of pattern generators, for which patterns were generated from memories, in which patterns were previously stored, in parallel, it was not possible to operate pattern generators having an operating function in parallel. A method, by which the order of execution of operation processing instructions is assigned to each of the pattern generators and operation processing instructions are accumulated and allows patterns to be generated at high speed by means of a pattern generator having an operating function. Specifically, the operating processing instructions are grouped and rearranged such that all the pattern generators execute instructions in parallel.
    Type: Grant
    Filed: July 29, 1987
    Date of Patent: February 27, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Ikuo Kawaguchi, Shuji Kikuchi, Chisato Hamabe
  • Patent number: 4901221
    Abstract: A method for programming a computer system having a display console for displaying images to control at least one of a virtual instrument and an instrument by the steps of displaying on the screen at least one first function-icon that references at least one first control module for controlling at least one first function; displaying on the screen at least one iteration-icon that references iteration control module for controlling multiple iterations of data flow; displaying on the screen at least one first input variable-icon that references at least one first input variable; displaying on the screen at least one first output variable-icon that references at least one first output variable; and assembling on the screen a first acyclic data flow diagram including the at least one first function-icon and the at least one iteration-icon and the at least one first input variable-icon and the at least one first output variable-icon, such that the diagram displays a first procedure for producing at least one value
    Type: Grant
    Filed: April 14, 1986
    Date of Patent: February 13, 1990
    Assignee: National Instruments, Inc.
    Inventors: Jeffrey L. Kodosky, James J. Truchard, John E. MacCrisken
  • Patent number: 4901275
    Abstract: A unit for providing an interface between analog input signals and a digital data processing system bus includes a plurality of analog input channels, sample-and-hold circuits, and an analog-to-digital converter. An optical isolation circuit couples the output of the analog-to-digital converter to a dual-port RAM. The gain of each analog input channel is programmable, as is the address of each input channel in the RAM. Thus the channels can be read in any desired order, and different input voltage ranges can be programmed for each channel. The RAM can be read by an external data processing system via a digital system bus.
    Type: Grant
    Filed: September 4, 1987
    Date of Patent: February 13, 1990
    Assignee: Burr-Brown Limited
    Inventors: Ian Hardie, David Vine
  • Patent number: 4896261
    Abstract: A system (10) for scheduling serial message transmission on a single bus (11) having a plurality of messages to be sent stored in memory (21) with each message located between associated start and end message addresses (START, END). A message list or queue (28) of the messages to be sent is formed and stored in memory (22) wherein the list comprises message pointer blocks (27) associated with each of the messages. Each pointer block includes at least the message start and end addresses, the message unique ID code (MID), the message priority (PRI), the address of the message pointer block associated with the next message to be sent (NEXT) and the address of the message pointer block associated with the previous message to be sent (PREV). A message transmission apparatus (16, 17, 18, 19) then sequentially serially transmits the messages on the bus in accordance with the message transmission order specified in the message list.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: January 23, 1990
    Assignee: Motorola Inc.
    Inventor: Michael P. Nolan
  • Patent number: 4894796
    Abstract: An automatic transfer switch with microprocessor and a display which includes clusters or combinations of display cells. There may, for example, be sixteen display cells for a 16-word display. The display cells are driven by two serially connected shift registers, the input of the first of which is interconnected with the microprocessor. Sixteen digital words are supplied in sequence to the shift registers. One portion of the digital word is then provided in parallel to each of the display cells simultaneously but another portion of the word is supplied to an encoding device which tells which of the sixteen display cells will display that word. One 16 word message requires sixteen reiterations performed at high speed so that it appears that all sixteen display devices are actuated simultaneously to display one multi-word message.
    Type: Grant
    Filed: March 17, 1986
    Date of Patent: January 16, 1990
    Assignee: Westinghouse Electric Corp.
    Inventors: Joseph C. Engel, James L. Lagree
  • Patent number: 4894798
    Abstract: A word processing apparatus is capable of detecting the entry of a function or operation during keying of the text into memory, which requires an operator intervention such as the changing of the print element or the changing of the format parameters. Upon the detection of that condition, an automatic operation is invoked by the software process to insert into the text string and memory a stop code. This insures that the playout of the stored text will be interrupted to permit the operator to perform the same or related operation at the same relative position in the text.
    Type: Grant
    Filed: June 20, 1986
    Date of Patent: January 16, 1990
    Assignee: International Business Machines Corporation
    Inventors: Marguerite H. Doyle, Roger W. Early, Steven R. Myers, Terrence W. Ringle, David R. Smith
  • Patent number: 4891754
    Abstract: A microinstruction sequencer capable of directing an arithmetic-logic unit to conduct conditional operations is disclosed and generally includes a ROM and a selection circuit. The ROM has a memory of m bits wide and n words long, wherein for an m bit wide word in the ROM which defines a conditional operation, a first plurality of bits of the m bits are allocated to a first set of bits for instructing the arithmetic-logic unit as to the function it is to perform, a second plurality of bits of the m bits are allocated to a second set of bits for instructing the arithmetic-logic unit as to the function it is to perform, and a third plurality of bits of the m bits are allocated to a set of control bits. The selecting circuit selects one set of bits from at least the first and second set of bits, and includes a controller for receiving the control bits and controlling the selection by the selection circuit in response thereto.
    Type: Grant
    Filed: July 2, 1987
    Date of Patent: January 2, 1990
    Assignee: General DataComm Inc.
    Inventor: Charles P. Boreland
  • Patent number: 4868738
    Abstract: An improved virtual memory computer system comprising a main processing unit for executing application and operating system software without virtual memory code and independently of virtual memory operation. A dedicated second processing unit is provided for maintaining a memory map, which translates addresses in the main processing unit address space into physical memory addressess of a primary memory. A network interface allows pages or segments of data from a secondary memory connected to a communications network to be transferred into the primary memory in a manner transparent to the operation of the main processing unit. A direct memory access (DMA) circuit transfer the header portion of a network-transferred page of data into a separate auxiliary addressable memory for storage of network overhead information, while the useful data portions of the page are stored directly in locations in the primary addressable memory.
    Type: Grant
    Filed: August 15, 1985
    Date of Patent: September 19, 1989
    Assignee: Lanier Business Products, Inc.
    Inventors: John W. Kish, John S. Alcorn, David B. Burleson
  • Patent number: 4868783
    Abstract: A system for interconnecting an intelligent controller to a plurality of terminal devices includes a software module, a microprocessor and a device adapter having a plurality of output ports. The system operates under the control of said software module. When the system is powered up, a status for the output ports is assumed and tested under control of a configuration register. If the test is successful, the terminal port remains in that state; if unsuccessful, the state of the terminal port is reversed. The system permits an exchange of operating modes in the terminal devices associated with one port without adversely affecting operation of the remaining ports in the system.
    Type: Grant
    Filed: June 15, 1987
    Date of Patent: September 19, 1989
    Assignee: International Business Machines Corporation
    Inventors: Gary D. Anderson, Gerald J. Hladik, Lawrence G. Mosher, Raymond L. Ricci, Henry Yeh
  • Patent number: 4862349
    Abstract: A method for extracting and replacing Control Block information in an operating system. An extract replace table is provided to permit application programmers to locate and in certain instances replace items contained in operating system Control Blocks. The user of the application program need not know the precise location of information contained in operating system Control Blocks. The extract/replace table will, upon formulating a request for either extracting or replacing Control Block items, find the requested items and read or replace them. Revisions of operating system programs may be made without regard to the new location of control items. The system user will locate and replace Control Block items by addressing the updated extract/replace tables.
    Type: Grant
    Filed: October 19, 1987
    Date of Patent: August 29, 1989
    Assignee: International Business Machines Corporation
    Inventors: Dennis J. Foreman, David A. Hellenga, Richard K. Hill
  • Patent number: 4858175
    Abstract: In a monolithic semi-custom LSI, different types of standard LSI logic sections, each having a predetermined logic configuration and wiring pattern, and each serving as an independent LSI chip; glue circuits such as an SSI and an MSI which have design standards suitable for the same process conditions as those of the standard LSI logic sections, and which constitute a peripheral circuit section of the standard LSI logic sections; a mask pattern section having a wiring region for arbitrarily connecting terminals of the standard LSI logic sections and the peripheral circuit section, and a bonding pad section formed to surround the standard LSI logic sections and the peripheral circuit section to connect them to lead wires, are arranged to minimize the chip size. These constituting elements constitute common hardware as a master. The elements are connected through a single- or multi-layer wiring pattern.
    Type: Grant
    Filed: September 27, 1985
    Date of Patent: August 15, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuyuki Sato
  • Patent number: 4847756
    Abstract: A data transmission system includes a host CPU having an output terminal for repeatedly producing a predetermined number of data blocks in a predetermined sequence in a repeated manner. Each data block is defined by a sequence code for identifying each data block and specific data followed by the sequence code. A plurality of slave CPUs are provided. The host CPU is connected to each slave CPU through a bus structure for the mutual data transmission. Each slave CPU receives all the data blocks and selectively extracts only the necessary data for use in each slave CPU and produces data from its output terminal at a given period within one cycle of the predetermined sequence. The given period for one slave CPU differs from that of another slave CPU, thereby transmitting data to the host CPU without any interferences.
    Type: Grant
    Filed: June 12, 1987
    Date of Patent: July 11, 1989
    Assignee: Minolta Camera Kabushiki Kaisha
    Inventors: Masazumi Ito, Kenji Shibazaki
  • Patent number: 4843593
    Abstract: A word processor for setting print out format for each line of a document to be printed by a decorative character printer. The word processor can format data by using various format data bits. The decorative character printer uses decorative character font-identifying bits. The word processor has a device for selecting either a format data input mode or a word data input mode. The format data or word data can be input and stored in the word processor. It will then be determined whether the format data includes decorative character-related data at the head or tail of a line of word data. Decorative characters can then be developed if such data is present in a line of word data.
    Type: Grant
    Filed: August 21, 1986
    Date of Patent: June 27, 1989
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hirofumi Yanaru, Hiroki Maruido
  • Patent number: 4841437
    Abstract: A multifunction test apparatus which is capable of performing total communication network measurments and includes a primary processor linked to a number of dependent processors. The primary processor plays a number of different roles in the functioning of the test system, which roles require substantial interaction between the primary processor and dependent processors. In some test configurations, the primary processor becomes a dependent processor. In other configurations, the primary processor is timeplexed and interleaved with the operation of the dependent processors in performing subfunctions for the dependent processors. The architecture also provides for direct communication and resource sharing between the dependent processors. In another aspect of the subject invention, the primary processor performs overflow calculations for the dependent processors. Finally, the device is arranged such that all test functions are displayed with consistent screen formats.
    Type: Grant
    Filed: September 18, 1985
    Date of Patent: June 20, 1989
    Assignee: LP COM
    Inventors: Andre Lubarsky, Richard E. Pospisil