Abstract: Apparatus for performing vector operations on the data elements of vectors includes a vector processor for performing arithmetic operations on the elements, a vector memory for storing the data elements for use by the processor, the vector memory having a port for reading and writing, and at least one staging register interposed between the vector memory port and the processor; the port and the register are each sufficiently wide to span more than one data element. As a result, on average fewer than one read or write operation per data element is required to access the vector memory via the port. Access to the vector memory port (i.e.

Abstract: A database of interests is maintained in a distributed computing system to register the individual interests of users in centrally stored non-textual media files, such as digital voice, music, scanned-in image, and video files. Uniquely named piece table style persistent data structures are employed to give users controlled access to the underlying non-textual media files by embedded name reference to such piece tables in ordinary messages or text files, so a database of piece tables is also maintained. A garbage collector periodically enumerates the interest database to delete interest entries which have been invalidated. Aged piece tables are deleted from the reference database when there no longer are any recorded interests referring to them, and non-textual media files are deleted to reclaim the storage space allocated to them when there no longer are any piece tables referring to them.

Abstract: An improved virtual memory computer system comprising a main processing unit for executing application and operating system software without virtual memory code and independently of virtual memory operation. A dedicated second processing unit is provided for maintaining a memory map, which translates addresses in the main processing unit address space into physical memory addressess of a primary memory. A network interface allows pages or segments of data from a secondary memory connected to a communications network to be transferred into the primary memory in a manner transparent to the operation of the main processing unit. A direct memory access (DMA) circuit transfer the header portion of a network-transferred page of data into a separate auxiliary addressable memory for storage of network overhead information, while the useful data portions of the page are stored directly in locations in the primary addressable memory.

Abstract: A data transmission system includes a host CPU having an output terminal for repeatedly producing a predetermined number of data blocks in a predetermined sequence in a repeated manner. Each data block is defined by a sequence code for identifying each data block and specific data followed by the sequence code. A plurality of slave CPUs are provided. The host CPU is connected to each slave CPU through a bus structure for the mutual data transmission. Each slave CPU receives all the data blocks and selectively extracts only the necessary data for use in each slave CPU and produces data from its output terminal at a given period within one cycle of the predetermined sequence. The given period for one slave CPU differs from that of another slave CPU, thereby transmitting data to the host CPU without any interferences.

Abstract: A word processor for setting print out format for each line of a document to be printed by a decorative character printer. The word processor can format data by using various format data bits. The decorative character printer uses decorative character font-identifying bits. The word processor has a device for selecting either a format data input mode or a word data input mode. The format data or word data can be input and stored in the word processor. It will then be determined whether the format data includes decorative character-related data at the head or tail of a line of word data. Decorative characters can then be developed if such data is present in a line of word data.

Abstract: A multifunction test apparatus which is capable of performing total communication network measurments and includes a primary processor linked to a number of dependent processors. The primary processor plays a number of different roles in the functioning of the test system, which roles require substantial interaction between the primary processor and dependent processors. In some test configurations, the primary processor becomes a dependent processor. In other configurations, the primary processor is timeplexed and interleaved with the operation of the dependent processors in performing subfunctions for the dependent processors. The architecture also provides for direct communication and resource sharing between the dependent processors. In another aspect of the subject invention, the primary processor performs overflow calculations for the dependent processors. Finally, the device is arranged such that all test functions are displayed with consistent screen formats.

Abstract: In an information processing method and system including a secondary storage, a primary storage for storing data blocks of the secondary storage and a directory containing control information for the data blocks stored in the primary storage, the directory is consulted to determine whether a desired data block is in the primary storage, and if it is, the data block is read from the primary storage. The control information of the directory contains pairs of addresses on the primary storage of the data blocks stored in the primary storage and the addresses on the secondary storage.

Abstract: An asynchronous FIFO incorporates a series of interconnected cells alternately oppositely inverted to provide forward and retrograde data paths, so as to selectively establish virtual flip flops as needed at interfaces between cells. Each cell combines an inverting amplifier for data, switch structure and a binary control for the switch structure to provide the data path. The controls are interconnected in a sequence along with logic to set the state of each control according to an instruction: copy the state of your predecessor in the sequence if the states of your predecessor and successor differ, otherwise hold your present state.

Abstract: A computer which achieves highly parallel execution of programs in instruction flow form, as distinguished from data flow form employing a unique computer architecture in which the individual units such as, process control units, programmable function units, memory units, etc., are individually coupled together by an interconnection network as self-contained units, logically equidistant from one another in the network, to be shared by any and all resources of the computer. All communications among the units now take place on the network. The result is a highly parallel and pipelined computer capable of executing instructions or operations at or approaching full clock rates.Each process control unit initiates its assigned processes in sequence, routing the first instruction packet of each process through the network and addressed memories and function units back to the initiating process control unit where it is relinked with its process.

Abstract: In a multiprocessor, multiprogrammed data processing system employing virtual addressing, apparatus and method are provided for selecting a page frame in a main memory unit to be replaced by a new page frame of logic signal groups required by a processor. Rather than utilize an algorithm implemented in a series of logical decisions determined by a software procedure, the present invention provides for a single instruction that uses the status signals included with a page descriptor to address an entry in a table of resulting status signals. The relationship between the status signals and the table entries implements the algorithm. The table with entries of resulting status signals is associated with the instruction and is stored in the processor when the instruction is prepared for execution by the processor. The resulting status signals are stored with the page descriptor, replacing the original status signals.

Abstract: An editing system for use in a virtual machine environment in which two virtual machines having corresponding virtual storage areas are operatively related to one another. The editing system allows a first virtual machine to print, display, modify and otherwise control and process information stored in a second virtual machine storage area.

Abstract: An optimizer-code generator for use in a data base system. The optimizer-code generator employs a component called a scan analyzer for performing implementation-dependent analysis and providing implementation-dependent query code. The optimizer-code generator receives a query in logical tree form. It first optimizes the logical tree. In so doing, it provides information from the logical tree to the scan analyzer, which specifies what methods are available for accessing information required for the query and what each of the available methods costs. The optimizer-code generator uses the cost information in its optimization of the logical tree and specifies the access methods to be used in the logical tree. The code generator then uses the logical tree to generate query code. In so doing, it provides the specifications of the access methods to the scan analyzer, which returns query code for the access method.

Abstract: A virtual processor mechanism and specific techniques and instructions for utilizing such virtual processor mechanism within an SIMD computer having numerous processors, and each physical processor having dedicated memory associated therewith. Each physical processor is used to simulate multiple "virtual" processors, with each physical processor simulating the same number of virtual processors. The memory of each physical processor is divided into n regions of equal size, each such region being allocated to one virtual processor, where n is the number of virtual processors simulated by each physical processor. Whenever an instruction is processed, each physical processor is time-sliced among the virtual memory regions, performing the operation first as one virtual processor, then another, until the operation has been performed for all virtual processors. Physical processors are switched among the virtual processors in a completely regular, predictable, deterministic fashion.

Abstract: A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.

Abstract: A single interface circuit for use with a computer peripheral having drivers and receivers which may be configured to be compatible with either short line input/output cables or long line input/output cables. Jumpers are provided to configure the interface circuit as desired.

Abstract: Calculator having a keyboard in which one or more keys have labels created by a display and subject to changing interactively as the user desires. Typically, advanced scientific-programmable calculators may have too many functions to be adequately included on the keys of the keyboard associated therewith. In such calculators, certain functions require a plurality of keys to be actuated in order to be performed. Thus, such keyboards tend to be cluttered an confusing to the user. Thus, a keyboard is proposed having a small number of keys labeled with different functional labels as the user proceeds through a menu or tree structure containing all the desired functions. Keys in a certain group of keys on the keyboard are thereby subject to redefinition or relabeling so as to provide a variety of functions.

Abstract: A microprocessor based system (10) includes a central processing unit (CPU) (12) that controls the operation of a display (20) through a controller (22). System storage is provided with a read only memory (16) and random access memory (14). A reference clock signal is generated by a clock generator (26) which is input to a clock control circuit (24). The control circuit (24) generates a CLK signal that is connected to the clock input of the CPU (12). The control circuit (24) is operable to reduce the rate of the clock input to the CPU (12) when accessing the controller (22) which has a slower speed of operation than the random access memory (14). The control circuit (24) includes a programmable counter (38) for generating a gating signal after counting a predetermined number of cycles of the reference clock signal and initiating a count cycle only after generation of the gating signal.

Abstract: A computing system having a non-volatile memory with locations with store data and are physically accessible such that the locations can be human visually readable to determine the data values stored therein. The non-volatile memory is operatively coupled to the computing system so that the computing means can write data into the non-volatile memory.A postage meter employing this system is adapted to be energized by an external source of operating power and includes a postage printing mechanism for printing postage and a computing system coupled to said postage printing mechanism for accounting for postage printed by the printing mechanism. A non-volatile memory for storing data is operatively coupled to the computing system and includes locations for storing data, critical postage accounting and other data when the postage meter is not energized by the external source of operating power.

Abstract: A coprocessor architecture specifically adapted for parallel operation as one of an array of coprocessors is described. Each of the coprocessors of the array are commonly responsive to a host processor. The coprocessor architecture preferably includes a selector for enabling the responsiveness of the coprocessor architecture to instructions from the host processor including an enabled responsiveness unique among the plurality of coprocessors and enabled responsiveness that is in common with that of the plurality of the coprocessors. The coprocessor architecture further includes a microengine for qualifying the responsiveness of the coprocessor to instructions provided by the host processor including qualification of the enabled responsiveness of the coprocessor architecture as provided for by the selector.

Abstract: A print engine data interface for sequentially accessing locations in a full page bit map for either retrieving the data therein and forwarding it to a print engine for subsequent printing, or for issuing a refresh command to refresh the data. A bit map address counter generates address location in the full page bit map that the print engine data interface accesses. A scan offset adjustment circuit in combination with a refresh and read/write arbitration logic circuit and the bit map address counter are provided so that the print engine data interface only accesses address locations for read/write retrieval that contain printing instructions to be forwarded to the print engine. The bit map locations that do not include printing instructions for forwarding are thus accessed only for refreshing. The print engine data interface further includes a parallel-to-serial converter unit to put the retrieved data in a form so that it can be forwarded in the usable state to the print engine.