Abstract: A single board multiple option card for expanding the versatility of a host computer includes an onboard microprocessor, a digital signal processor and a switched memory device. The switched memory is accessible by the onboard microprocessor and the digital signal processor under the control of the onboard microprocessor. The card further includes an analog signal interface having a plurality of switches, the positions of which are controlled by the onboard microprocessor. As a result, multiple options are provided by varying the positions of the switches. Typically, such options may include: "Invisible Keyboard"; "Voice Command Over Telephone Lines"; "Voice Store and Forward Over the Telephone"; "Voice Record and Playback"; and "Hands-free Telephone".

Abstract: A data processing system which contains a multi-level storage hierarchy, in which the two highest hierarchy levels (e.g. L1 and L2) are private (not shared) to a single CPU, in order to be in close proximity to each other and to the CPU. Each cache has a data line length convenient to the respective cache. A common directory and an L1 control array (L1CA) are provided for the CPU to access both the L1 and L2 caches. The common directory contains and is addressed by the CPU requesting logical addresses, each of which is either a real/absolute address or a virtual address, according to whichever address mode the CPU is in. Each entry in the directory contains a logical address representation derived from a logical address that previously missed in the directory. A CPU request "hits" in the directory if its requested address is in any private cache (e.g. in L1 or L2). A line presence field (LPF) is included in each directory entry to aid in determining a hit in the L1 cache.

Abstract: A channel apparatus including a transfer controller responsive to an input data transfer command, for translating virtual block address data designated by a channel command word (CCW) into RBA data to store the translated RBA data. The CCW commands the DMA transfer of the data over a plurality of subsequent blocks of the external memory. The translated RBA data are written in a real address storage section in a write mode. The controller outputs a transfer start instruction to a DMA transfer section after outputting an initial value of a DMA address to a DMA transfer section and writing a predetermined amount of the RBA data to the storage section. The DMA transfer section performs the DMA transfer of the data to the external memory in a read mode in accordance with the transfer start instruction while the data is being input from the external device. The transfer section generates a memory request every time performing the DMA transfer of one word of the data.

Abstract: A 32-bit central processing unit having a six-stage pipeline architecture with a cache memory and memory management unit all provided on a single integrated circuit (I.C.) chip but without any peripheral interface input/output circuits, clock or similar circuits on the chip in order to utilize the limited I.C. area for implementing the processor functions that most directly affect speed of operation and other performance factors.

Abstract: An interface system having a plurality of signal lines connected between a plurality of input terminals of a control circuit and a plurality of output terminals of a host computer. A plurality of resistor elements each have one end connected to a corresponding one of the plurality of signal lines and the other ends connected in common to a second of a pair of first and second terminals, of which the first terminal is connected to a power source to supply electric power when the terminal pair is short-circuited by a jumper disposed between the first and second terminals. A plurality of diode elements have anodes connected to the second terminal of the terminal pair and cathodes connected to the other ends of the plurality of resistor elements. The resistor elements are electrically interrupted without physically removing the resistor elements by opening the path between the first and second terminals.

Abstract: A microprocessor controlled mass storage controller is used as an interface for mass storage devices which are shared by a plurality of stand-alone microcomputer systems. The microprocessor controlled mass storage controller has a system interface which maintains communications with a host microcomputer; a dedicated microprocessor which maintains the internal control of the controller and a network interface which maintains an access to the external network. Data transparency and integrity are achieved through the simulation by the controller of the mass storage device characteristics and responses.

Abstract: A data processor for executing a program of instructions stored in a program memory controlled by a program counter. To execute a loop control instruction, calling for repeated execution N times of a sequence of "i" instructions, the processor includes a loop circuit having an instruction counter which counts execution of the instructions in the loop sequence and produces an end-of-sequence signal upon each completion of the loop, a register which refreshes the program counter with the address of the first instruction in the loop in response to each end-of-sequence signal, and a loop counter which counts the number of completions of the loop and delivers a signal indicating the end of the loop portion of the entire program and enabling the program counter to continue on with the rest of the program. The delay in loop execution permits initializing of registers in the data processor so as to permit pipeline execution of the loop instruction.

Abstract: An information processing system includes a processor responsive to instructions for performing operations. The processor includes instruction queue for fetching and storing instructions in advance of execution and the system is responsive to certain of the instructions for causing execution of a corresponding sequence of instructions. A prefetch monitor includes circuitry for detecting instructions which may result in the execution of a corresponding sequence of instructions. The prefetch monitor further includes an instruction substitution circuit which is responsive to the detecting circuitry for inhibiting the reading of following instructions from a memory to the processor and is responsive to instruction fetching operation of the processor for reading null instructions to the processor.

Abstract: Apparatus for controlling the use of software in accordance with authorized software license limits, including a limit of the number of concurrent usages of a particular software in a computer system having one or more operator terminals and a central processor containing the software. The apparatus includes a receiver that monitors usage requests from the software in the central processor. A microprocessor based controller accesses authorized use data stored in an EEPROM. Depending on the propriety of usage requests, the controller and an interruptor and transmitter coupled to the central processor and its software prevents operation of the software and/or provides warning messages on the terminal screen.

Abstract: A multi-level priority interrupt system is used for controlling the access of input/output control devices to a host computer which is connected to the devices and controls their operation. The input/output control devices each of which is contained on a different LSI chip, output different levels of interrupt requests to the host computer. During operation, each input/output control device outputs an interrupt signal of a frequency determined by a level of an interrupt to be sent to the host computer. The interrupt signal is supplied from one external terminal of the input/output control device. Upon receipt of the interrupt signals, the host computer determines a priority of the interrupt from the frequency of the signal and then executes a corresponding interrupt routine.

Abstract: A bus control system for a common data bus between a central processing unit (CPU) and a plurality of peripheral devices has an address decoder which decodes address data from the CPU to output one of a chip selection signal S.sub.c and a plurality of chip selection signals S.sub.1 to S.sub.n. The chip selection signal S.sub.c brings all the devices into operative conditions simultaneously, while each of the chip selection signals S.sub.1 to S.sub.n brings a respective one of the devices into an operative condition. Each of the devices has a first register which is responsive to a corresponding one of the chip selection signals S.sub.1 to S.sub.n to store data appearing on predetermined bit-lines of the data bus and first and second gate circuits. When the CPU causes the address decoder to output the chip selection signal S.sub.c in a write mode, the first gate circuit of each device passes data appearing on the bit-line of the bus designated by the data in the first register into a second register.

Abstract: A magnetic tape system includes a driving unit (1) including a magnetic head (14), reels (11, 12) for winding a magnetic tape (16) thereon and a drive portion for driving the reels; a drive control unit (2, 20, 21) for controlling the drive unit; and a prefetch control unit (3) having a first memory for prefetching a plurality of commands from the host controller and a second memory for temporarily storing data from the host controller or data read out from the magnetic tape. The drive unit is operated through the drive control unit according to the commands stored in the first memory and the results of the operation are reported to the host controller.

Abstract: The present invention is directed to time-sharing computer system which includes a host computer system which operates in response to a host TSS command, a terminal computer system which is connected to the host computer system through a line and operates in response to a terminal TSS command, and a plurality of terminals which are connected to the terminal computer system. In this time-sharing system, the data processing in a terminal computer in response to a terminal TSS command input and the subsequent data processing in the host computer system in response to a host TSS command input can be carried out freely when the terminal is in a state of interaction with the host computer, without carrying out an end command of the host TSS a mode exchange operation. For this purpose, the system adopts the concept of a multiplexed TSS, which enables plural sessions to be simultaneously executed by the host computer system and the terminal computer system.

Abstract: Techniques for a logic analyzer instrument that permit the acquisition of digital samples from a plurality of logic signals in a large mainframe computer, or other system under test, in a manner that the signals can be reconstructed for viewing and analysis of the relationship between them. Edges of the signals are located, during their reconstruction, with many times higher resolution than that of the sampling clock. A plurality of sample records, asynchronously timed, are taken of the logic signals from the system under test, and the samples are combined in a way that locates logic signal edges with precision.

Abstract: A timing signal generating apparatus is used for testing ICs, particularly ICs having more than two enable input terminals. Data representative of the time of occurrence of a timing signal with respect to a reference signal is stored in a memory. In a first cycle, data is combined by an arithmetic unit with data stored in another memory. The latter data represents a predetermined desired variation in the time of occurrence of the timing signal. The output of the arithmetic unit is then stored in a temporary memory and combined with the data representative of the predetermined variation in time of occurrence of the timing signal. The time of occurrence of the timing signal is determined by the output of the arithmetic unit. A timing signal is thus produced over an almost arbitrary range of delays with respect to the reference signal.

Abstract: A data processing system in which, when a magnetic tape device is required for execution of a job, a group of magnetic tape devices is designated and an appropriate one of the magnetic tape devices in the designated group is selected and allocated to the job. In order to start the execution of the job as early as possible, status data indicating whether a magnetic tape is loaded in a device and is being rewound or not is read, and one of the magnetic tape devices in the designated group, which is not loaded with a magnetic tape, is selected to have a top priority. In the absence of such a device, a magnetic tape device loaded with a magnetic tape which is not being rewound is selected in preference to the others.

Abstract: A monolithic integrated digital circuit including at least one circuit for the serial data processing of multi-digit data signals synchronized to a clock system, the serial data processing circuits using a clock signal coming from a clock oscillator which is also integrated. The clock oscillator includes an odd number of ring-connected inverting stages. The output of the oscillator is provided to a counter. When the counter counts a number of pulses equal to the number of digits of the output signal of the data processing circuit, the counter stops the clock oscillator. The system clock signal is applied to both the reset input of the counter and the synchronizing input of the data processing circuit.

Abstract: A n-channel memory management circuit operates as an interface unit between a microprocessor, which microprocessor is normally capable of addressing only 64K bytes of memory, to provide expandable memory configurations with a memory capacity of at least 128K bytes of read only memory (ROM) and 128K bytes of random access memory (RAM) which are directly accessed by the microprocessor in 64K bytes blocks or "windows" consisting of smaller size non-contiguous blocks from the entire memory configuration.

Abstract: A random access memory is used to realize a sequence of delay lines (40, 46, 48, 50). The delay lines are linked so that a common end point of two delay lines can be addressed in a read/modify/write operation. Furthermore, the address step between two successive data elements of the delay line is increased, so that the new address must be calculated modulo the length of the consecutive zone reserved for the delay lines. It has been found that in many cases the incrementation step between the various read addresses has a value which can be expressed in a number of bits which is smaller than the number of bits necessary to express the length of the consecutive memory zone itself.

Abstract: A dynamic RAM memory refresh circuit is used with a microprocessor. In a small telecommunication switching system, a microprocessor shares access to memory with the dynamic RAM refresh circuit. Since circuitry size is of paramount importance, this circuit may be implemented with CMOS gate array technology. Since memory access is shared by the microprocessor and the dynamic RAM refresh circuit, processor through-put is affected. However, due to the speed of the dynamic RAM refresh circuit, the microprocessor real-time through-put is degraded only from 2 to 5 percent. A row of dynamic RAM memory is refreshed during each memory access by the refresh circuit, so that during a 2 millisecond inteval all dynamic RAM memory is refreshed. In addition, the dynamic RAM refresh circuit provides a strapping option to allow operation of the refresh circuit in conjunction with microprocessors of different clock frequency.