Patents Examined by Florin Munteanu
  • Patent number: 4754425
    Abstract: A dynamic RAM memory refresh circuit is used with a microprocessor. In a small telecommunication switching system, a microprocessor shares access to memory with the dynamic RAM refresh circuit. Since circuitry size is of paramount importance, this circuit may be implemented with CMOS gate array technology. Since memory access is shared by the microprocessor and the dynamic RAM refresh circuit, processor through-put is affected. However, due to the speed of the dynamic RAM refresh circuit, the microprocessor real-time through-put is degraded only from 2 to 5 percent. A row of dynamic RAM memory is refreshed during each memory access by the refresh circuit, so that during a 2 millisecond inteval all dynamic RAM memory is refreshed. In addition, the dynamic RAM refresh circuit provides a strapping option to allow operation of the refresh circuit in conjunction with microprocessors of different clock frequency.
    Type: Grant
    Filed: October 18, 1985
    Date of Patent: June 28, 1988
    Assignee: GTE Communication Systems Corporation
    Inventor: Nataraj Bhadriraju
  • Patent number: 4752872
    Abstract: An arbitration device for enabling a common resource to be shared by a plurality of processors, all connected by a common bus and each processor having a certain access priority. When more than one processor requests access to the resource, the highest priority processor request signal is latched and access is granted while the other requesting processor's latches remain set (access not granted). If two processors request access while the resource is busy, then only the latch of the processor having the highest priority of the two will be reset when the bus becomes available, and that processor will gain access.
    Type: Grant
    Filed: June 17, 1985
    Date of Patent: June 21, 1988
    Assignee: International Business Machines Corporation
    Inventors: Daniel Ballatore, Simon Huon, Jean-Marie Munier
  • Patent number: 4748560
    Abstract: Plural stations are connected to two independent serial buses and they are permitted to occupy a first serial bus in a predetermined order under control of a bus controller. A second serial bus is used for transmitting to the bus controller an urgent bus occupancy request issued by any of the stations. Upon receipt of the urgent bus occupancy request, the bus controller permits the request-issuing station to occupy the first serial bus regardless of the predetermined order, thereby insuring a fault-free operation of the system for transmitting data between the stations.
    Type: Grant
    Filed: October 11, 1985
    Date of Patent: May 31, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Isaburou Kataoka
  • Patent number: 4742450
    Abstract: A method for facilitating the interchange of data in a UNIX* file between two UNIX processes being run concurrently on two virtual machines in a page segmented virtual memory virtual machine type data processing system. A Shared Copy-On-Write (SCOW) command is created for the UNIX type operating system which when executed in response to a system call from one processes causes the specified UNIX file to be mapped to a unique segment of the virtual memory. A map node data structure is established for storing the ID of the unique segment and for maintaining a count value of the number of user sharing the unique segment. A system call to the SCOW command by the second process involving the same UNIX file checks the map node data structure to see if the file is currently mapped for the SCOW mode. Subsequent instructions in the application programs which are run concurrently on the virtual machines operate on the copy of the file in the unique segment so that any data that is changed, i.e.
    Type: Grant
    Filed: January 16, 1986
    Date of Patent: May 3, 1988
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Duvall, Anthony D. Hooten, Larry K. Loucks
  • Patent number: 4742451
    Abstract: A central processor unit for a digital data processing system that processes prefetched instructions including a conditional branch instruction. The processor includes a fetch unit that has separate portions, one that retrieves operands and the other that retrieves instructions. When the fetch unit fetches a conditional branch instruction, it may continue to prefetch "branch not taken" instructions using the instruction fetch portion. The fetch unit initially uses the operand fetch portion to prefetch "branch taken" instructions. If it is determined that the branch is not taken, the prefetch operation is aborted, otherwise the prefetch operation is allowed to continue to provide the next instruction used by the processor.
    Type: Grant
    Filed: May 21, 1984
    Date of Patent: May 3, 1988
    Assignee: Digital Equipment Corporation
    Inventors: William F. Bruckert, Tryggve Fossum, John A. DeRosa, Jr., Richard E. Glackemeyer, Allan E. Helenius, John C. Manton
  • Patent number: 4740890
    Abstract: An apparatus for preparing and playing back a duplicated disk containing software as a program so that a customer will be able to use the disk for a predetermined trial period. The duplicated disk is impressed with information relating to this system in the form of a usage count, a locking status and an output code. The usage count is written on the disk and determines the number of times the disk can be used by a customer. The output code identifies a locking code whereby after the allocated number of uses is over, the vendor can unlock the disk to allow unlimited use. The lock code determines whether or not the disk is subjected to the above noted trial usage period. The usage count which is impressed on the disk is detected during each time the disk is used and the usage count is decremented by one until the predetermined number of uses has been accommodated.
    Type: Grant
    Filed: December 22, 1983
    Date of Patent: April 26, 1988
    Assignee: Software Concepts, Inc.
    Inventor: Tobin William
  • Patent number: 4739476
    Abstract: Method and apparatus for interconnecting the processing cells of a parallel processing machine configured in a two-dimensional rectangular array in which each cell includes a plurality of ports, each port having a unique port address, and a plurality of cells have similarly addressed ports. The cells are interconnected, via the cell ports, to form cell clusters having a central cell and eight neighboring cells such that a plurality of neighboring cells share a common connection to the central cell and further such that no two similarly addressed ports are coupled to one another. During a data transfer operation, in accordance with the single instruction multiple data (SIMD) format, each cell transmits data from one port and receives data from another port such that all cells transmit data from similarly addressed ports and receive data at similarly addressed ports to provide data transfer throughout the array in a uniform direction.
    Type: Grant
    Filed: August 1, 1985
    Date of Patent: April 19, 1988
    Assignee: General Electric Company
    Inventor: Charles M. Fiduccia
  • Patent number: 4737933
    Abstract: A general purpose register including two input ports and two output ports, each port being addressed by an independent addressing circuit. The general purpose register includes a number of internal registers, and the provision of four independent addresses enables data to be written into two internal registers while data is being read out of two internal registers. The general purpose register also includes circuitry for transferring data from the input ports directly to the output ports without entering the data into the internal registers. Interchanging of bytes of data input words is also accomplished by the general purpose register. The internal registers, the four independent addressing circuits, the data transferring circuitry and additional undedicated circuitry are integrated into a single chip.
    Type: Grant
    Filed: February 22, 1983
    Date of Patent: April 12, 1988
    Assignee: Storage Technology Partners
    Inventors: Michael Chiang, John J. Zasio, Tien-Lai Hwang
  • Patent number: 4733366
    Abstract: Logic circuitry for use in electrical apparatus for providing an interrupt signal to a controller when there is a power failure in the electrical apparatus. The logic circuitry is connected to a bus from the controller. When the logic circuitry receives a power failure signal, it sets an interrupt state register and provides an interrupt signal on the bus as long as the interrupt state register is set. If the power failure signal no longer indicates a power failure, the logic circuitry responds to a signal from the controller indicating that the interrupt has been received by resetting the interrupt state register, thereby ending the interrupt. However, if the power failure signal is still active, the logic circuitry will not reset the interrupt state register in response to the signal from the controller.
    Type: Grant
    Filed: May 16, 1983
    Date of Patent: March 22, 1988
    Assignee: Data General Corporation
    Inventors: Joseph P. Deyesso, Edward Gershenson, Louis A. Lemone, Mark C. Lippitt, John R. McDaniel, Paul F. Joseph
  • Patent number: 4731739
    Abstract: A memory apparatus which includes an intermediate store addressed by logical addresses and a main store addressed by system addresses. The memory unit has a translator for translating logical addresses to system addresses. The translator includes a translation lookaside buffer having a system address store with first and second fields storing system addresses corresponding to each translated logical address and a control field including a flipper bit for indicating which one of the system addresses is the currently active real address. The control field also includes an eviction pending bit for each system address field. When the TLB is updated with a new translation, the previos active address field is marked with an eviction pending bit and the the previos inactive address field is written over with the new translation and marked active.
    Type: Grant
    Filed: October 17, 1985
    Date of Patent: March 15, 1988
    Assignee: Amdahl Corporation
    Inventors: Gary A. Woffinden, Donald L. Hanson
  • Patent number: 4729092
    Abstract: Data storage apparatus comprises a main store, for example a microprogram store, with an associated address generating circuit. In order to extend the capacity of the store, an additional store is provided, but because of physical limitations this is remote from the main store. To reduce delays in accessing data items from the additional store, a prediction circuit predicts the address of the next item to be required from the additional store and prefetches it. A control circuit checks whether the prefetched item is the correct one and, if it is not, causes a temporary hold-up in the operation of the address generation circuit to allow the correct data item to be fetched.
    Type: Grant
    Filed: May 17, 1985
    Date of Patent: March 1, 1988
    Assignee: International Computers Limited
    Inventor: John Lupton
  • Patent number: 4727474
    Abstract: The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.
    Type: Grant
    Filed: February 18, 1983
    Date of Patent: February 23, 1988
    Assignee: Loral Corporation
    Inventor: Kenneth E. Batcher
  • Patent number: 4725977
    Abstract: A cartridge programming system is provided for loading selected computer programs into a reprogrammable plug-in cartridge memory. A host computer controls a plurality of remote programming terminals. The terminals contain a library of programs. The consumer can select one and have it loaded into a blank cartridge. The terminal verifies the integrity of the copy and records the transaction. The host can send new programs to the terminals via dial-up telephone lines in response to the selection of a program not present in a particular terminal program library or in order to update the library of programs at each terminal and can request data on copying-transactions. Various security measures help assure accurate accounting of copies made, thereby assuring authors and their assignees that proper royalties can be billed.
    Type: Grant
    Filed: February 28, 1986
    Date of Patent: February 16, 1988
    Assignee: CPT, Ltd.
    Inventors: Hideki D. Izumi, Devender R. Beravol
  • Patent number: 4725944
    Abstract: Apparatus for providing a relatively constant clocking signal to a serial input/output device from a microprocessor regardless of whether the microprocessor is executing a normal instruction cycle or an extended cycle. A state machine is driven by the same clock which drives the microprocessor and a signal from the microprocessor indicating the presence of a normal or extended instruction cycle. The state machine and the clock which drives the microprocessor drive a clocking circuit which produces a first waveform if a normal instruction cycle is being executed, and a second waveform if an extended instruction cycle is being executed. Both waveforms are edge synchronized to the clock which drives the microprocessor.
    Type: Grant
    Filed: October 31, 1986
    Date of Patent: February 16, 1988
    Assignee: Tandem Computers Incorporated
    Inventor: Kenneth G. Koenig
  • Patent number: 4725978
    Abstract: A graphic pattern inputting apparatus composed of: a manually actuable inputting device mounted for movement parallel to a selected plane for producing sensor signals representative of the direction, parallel to the plane, and magnitude of manual force applied to the inputting device; a drive device operatively associated with the inputting device and responsive to control signals for moving the inputting device parallel to the selected plane; and a processing unit connected between the inputting device and the drive device for performing arithmetic operations on the sensor signals for producing control signals which are a function of the sensor signals, and for supplying the control signals to the drive device.
    Type: Grant
    Filed: May 29, 1984
    Date of Patent: February 16, 1988
    Inventor: Ichiro Fujioka
  • Patent number: 4722071
    Abstract: An intelligent compiler particularly useful for evaluating Boolean expressions such as those associated with ladder structures. True/false paths are defined through the expressions. In a first pass for the code generation, the start code for examining each element is set out. In a second pass the relative offsets for branching from one element to the next element along both the true and false paths are filled in. In practice, execution time for evaluating ladder structures is reduced by an order of magnitude over prior techniques which use source code and an interpreter.
    Type: Grant
    Filed: April 19, 1985
    Date of Patent: January 26, 1988
    Assignee: Pertron Controls, Corporation
    Inventors: Dirk I. Gates, David B. Rosen, Gary A. Jones
  • Patent number: 4714991
    Abstract: A data processing apparatus, which includes a microprogram control unit for producing control signals for the apparatus. Each microinstruction contains a number of control bits, and an address field. The address field addresses a control memory so as to read out a control word. Each control word specifies the way in which the control signals are mapped on to the control bits of the microinstruction. The output of the control memory controls switching logic which connects the control bits to the specified control signal lines. This variable mapping of the control signals allows the control signals to be packed into any available space in the microinstruction, thus reducing the required number of bits in the microinstruction without any significant loss of flexibility. Certain critical control signals however are derived from fixed positions in the microinstruction so as to avoid delays. These critical control signals are confirmed by validity signals from the control memory.
    Type: Grant
    Filed: February 1, 1985
    Date of Patent: December 22, 1987
    Assignee: International Computers Limited
    Inventor: John R. Eaton
  • Patent number: 4701843
    Abstract: A computer memory including a memory subsystem controller having a circuit for providing a plurality of block select signals and a raw address. A plurality of memory blocks is provided, with one of the memory blocks being provided for each of the block select signals from the memory subsystem controller. Each of the memory blocks includes random access memory (RAM) devices for storing data, and a refresh circuit for refreshing its associated RAM devices independent of the refreshing of the RAM devices of the other blocks. The refreshing of the refresh circuit occurs, if possible, when its associated memory block is not selected by its corresponding block select signal from the memory subsystem controller. A re-establishing circuit is included in each memory block which receives a row address from the memory subsystem controller and re-establishes the received row address in its RAM devices after they have been refreshed.
    Type: Grant
    Filed: April 1, 1985
    Date of Patent: October 20, 1987
    Assignee: NCR Corporation
    Inventor: Morris Cohen
  • Patent number: 4697250
    Abstract: Disclosed is a control unit including a flexible decoder unit providing control patterns for controlling functional units in data processing equipment. The control unit includes hardwired decoder logic which decodes a multi-bit key to provide primary decoded outputs as control patterns. The decoder unit also decodes one or more alternate decoded outputs for future use. The decoder includes a plurality of flexibility inputs which, when connected to an alternate decoded output, provide new control patterns and thus provides flexibility to the hardwired decoder. Because of the flexibility, the control patterns formed by the hardwired decoder can be readily changed. The flexible hardwired decoder is of great value, therefore, when design changes are desired in a computer.
    Type: Grant
    Filed: June 18, 1986
    Date of Patent: September 29, 1987
    Assignee: Amdahl Corporation
    Inventors: Hsiao-Peng S. Lee, Ulrich Spannagel
  • Patent number: 4695947
    Abstract: In an information processing system utilizing a virtual storage, an address translation look-aside buffer for translating a logical address into a physical address is provided to access the main storage by use of the translated physical address. The processing system has a storage control unit for controlling the operation of the address translation look-aside buffer and the main storage, which are connected with a common bus through which addresses and data are transferred on a time-division basis. The storage control unit has a bus control circuit for controlling the common bus so that addresses are transferred from the translation look-aside buffer and data is transferred to the main storage on the common bus at different times.
    Type: Grant
    Filed: February 6, 1984
    Date of Patent: September 22, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Ikeda, Kozi Nakamura, Toshihiro Okabe