Abstract: In an information processing system utilizing a virtual storage, an address translation look-aside buffer for translating a logical address into a physical address is provided to access the main storage by use of the translated physical address. The processing system has a storage control unit for controlling the operation of the address translation look-aside buffer and the main storage, which are connected with a common bus through which addresses and data are transferred on a time-division basis. The storage control unit has a bus control circuit for controlling the common bus so that addresses are transferred from the translation look-aside buffer and data is transferred to the main storage on the common bus at different times.

Abstract: A method of generating a backup copy of a database system. Modifications made to the database since the generation of a prior backup copy are summarized in a bit map on a page basis. When the next backup copy is made, only modified pages are transmitted and merged with the prior copy. Plural backup passes are made. New modifications are allowed to occur to the database on all but the last pass. Any database modification made at an address that has already been examined during a pass is backed-up during the next pass. Modifications are locked out at the beginning of the last pass to allow the final generation of a consistent and complete backup copy.

Abstract: A two control store scheme with instruction execution overlay is shown in a data processing system execution unit having a two-state pipeline. The first control store controls the first-stage facilities during the first cycle of instruction execution and points to the initial location of the second control store. The second control store controls the second-state facilities during the final cycle of instruction execution. The second control store also controls the facilities of both stages during the intermeidate cycles of instruction requiring more than two cycles to execute. Because the second control store controls only the second-stage facilities during the final cycle, execution of the first cycle of the following instruction can take place concurrently within the first-stage facilities under the control of the first control store.

Abstract: An interconnecting transparent serial bus for extending a parallel CPU domain to a parallel peripheral module domain includes a bidirectional serial protocol for transferring information between the CPU and one or more peripheral module controllers, referred to as rack masters. Each rack master provides a parallel path to any number of peripheral modules associated therewith. Serial bus protocol includes a frame line, defining a synchronous information exchange interval; a clock line, for propagating a synchronous information clock signal during the information exchange interval; a sync line, for propagating a sync signal to identify one or more discrete asynchronous information fields during the information exchange interval; and a signal line for propagating data, address, and control information between the CPU and its associated rack masters in serial fashion.

Abstract: A digital comparison system and technique enables an easy determination of the digital range within which digital addresses or data may fall or be selected. In one embodiment, the entire memory or addres space is divided into a predetermined number of sections, and each section's location in memory is defined by a predetermined first number of digits of the address. Likewise each address within a section is defined by a second predetermined number of digits of the address. A digital identifier is assigned to each section to define the position of a section with respect to a desired range. Digital identifiers are also assigned to each address within a section to fix the end points within each section. The outputs from memory devices storing the identifiers are coupled through a multiplexer which allows the position of a selected address to be identified as inside, outside, or an end point of a predetermined range.

Abstract: A reprogrammable plug-in semiconductor memory cartridge for use in a personal computer system, the cartridge being reprogrammed without removing the circuitry from the cartridge. The cartridge uses a keying-locking circuitry, such as a resistor-capacitor circuit having a unique time constant which must be detected by a cartridge programming system before allowing the programming operation to start. Thus access to a programming system program library is limited only to cartridges having the above-mentioned keying-locking circuitry. A cartridge retailer maintains a master program library and a limited number of such blank cartridges rather than maintaining a large inventory of programmed cartridges.

Abstract: A supervisory circuit for use in an integrated circuit to supervise the program execution of a processing unit is disclosed. The processing unit generates a restart signal at a particular duty cycle under proper program execution conditions and at an undesirable duty cycle under improper program execution conditions. The supervising circuit includes a capacitive or like circuit element for converting the restart signal into a signal representative of the duty cycle thereof and compares the generated signal to a reference window comprising upper and lower reference values. Should the generated signal exceed the boundaries of the window reference, a corresponding control signal is generated to change the circuit conditions and generate a reset signal to the processing unit to govern the program execution thereof to a prespecified point from which point program execution may continue upon removal of the reset signal.

Abstract: An electronic computer linkage interface control security system that allows a remote computer terminal to control the across to a main computer. The system includes a Computer Linkage Interface Control (CLIC) module that is coupled to the terminal and that generates and stores a random or pseudo-random coupling code that is unique to the terminal and unique for each communication session. The computer, in which the coupling code for the current communications session was stored during the previous session, accesses the current coupling code store in the CLIC module for comparison with the computer's previously stored code. If a match occurs, access by the terminal to the main computer is permitted.

Abstract: An interface circuit connects a computer and peripheral units. The interface circuit includes a battery power source that drives a signal conversion circuit. A detector circuit detects levels of signals received from the computer, the signals being indicative of a power ON/OFF status of the computer. A control circuit controls the operation of the signal conversion circuit so that the built-in battery source will not be dissipated while the computer is not in operation. The control circuit also inhibits operation of the signal conversion circuit when the detector circuit indicates that condition of the battery source has deteriorated.

Abstract: In a video computer system, an improved memory circuit is provided which is effective for delivering stored data only at appropriate instances, and which is also simpler and more reliable in design. In particular, the system preferably includes a bit-mapped RAM circuit which assumes a serial mode in response to both a row address signal and a suitable data output control signal, and which assumes a parallel or "random" mode when only the row address is received. Stored data is transferred to a parallel output terminal in the RAM circuit, or to a serial output terminal therein, depending upon the sequence of these signals as well as the column address and read signals, whereby the data output control signal is used for two separate and different purposes within the system.

Abstract: A stand-alone functional apparatus comprises a plurality of processing circuits which operate under the control of status data applied by a control circuit and possibly apply status data to the control circuit, more specifically a television receiver with the control circuit in the form of a microcomputer. To protect this microcomputer against external disturbance, a plurality of addressable nonvolatile memory locations are present in which auxiliary status data for at least one processing circuit are stored. A program store comprises a plurality of control programs and also a recovery program. The latter is made operative in response to a disturbance, causing the auxiliary status data to be applied to the relevant processing circuit(s). To enable the determination of a disturbance at least one of the control programs includes a check program.

Abstract: A data transfer control system which is provided between a main memory for storing programs, data and channel control blocks (CCB's) and I/O processors for controlling channels, for converting an address from the I/O processors to an address specifying the main memory, first address memory which is addressed by combination data of a first identification number identifying the I/O processors and a second identification number identifying the channel and stores a CCB start address of the main memory; second address memory which is addressed by the combination data and stores a start address in a data transfer section included in the channel control block; and a data controller in which, when the first and second identification numbers, a flag, and a relative address are received from the channels through the I/O processors, one of the first and second address memories is selected in accordance with the flag value, the data controller generating an address by adding the address read out from the selected memory

Abstract: A computer system network with host machines and local machines linked hierachically with each other, wherein if file I/O status flag in control table of a local machine is set to terminal operation replacement mode by command input by terminal user, a data I/O request issued by an application program in a host machine to a terminal connected to the local machine is implemented by the I/O operation on the file connected to the local machine in place of the I/O operation on the terminal.

Abstract: In a system including a central processor, central memory, and local video controller communicating with a video terminal, the video terminal including a terminal processor and a video memory for storing video information for displaying on the terminal screen, a change detect circuit is provided in the local video controller for detecting whenever a change has occurred in that portion of the central memory containing video information to be displayed on the terminal's video screen. Responsive to the change detect circuit, the local video controller sends updated video information to the video memory at the terminal.The change detect circuit reduces the workload on the system by sending only the updated video information to the terminal.The change detect circuit is capable of operation with a system employing multiple terminals each having multiple independent screen display areas.

Abstract: An improved video memory system includes a program memory, a display data memory, and a plurality of data fetchers. The data fetchers are used to indirectly address the display data in the display data memory. The data fetchers are programmed during vertical blanking so that selected display data is fetched at selected vertical display positions. During each scan line each data fetcher is "read" by: (1) decrementing a counter in the data fetcher; (2) comparing the counter value against preselected top and bottom values; and (3) using the counter value to indirectly address display data that is to be displayed on the current scan line if the counter value is between the top and bottom values. This relieves the host computer of having to keep track of the current vertical display position, thereby freeing it to use the saved computer cycles to produce more interesting viedo games with more complex display graphics.

Abstract: A computer connected to at least one peripheral includes a memory, a program control circuit, an internal keyboard and a signal input/output device. The memory stores a program. The program control circuit is provided for controlling the computer according to the program. The peripheral is an external memory, an external input device, or the like. The signal input/output device is provided for connecting the computer and the peripheral to communicate data. Serial bit data transfer through data lines is used to send command control signals from the computer to the peripheral and for transfer of data between the computer and the peripheral. Control signals are sent on a control line to control the transmittal and reception of the command control signals and the data. When an external keyboard is selected as a peripheral, the internal keyboard may be disabled.

Abstract: In a video terminal comprising a terminal processor communicating with a central processor, and a single-block non-interleaved video memory for storing video information for displaying on the terminal screen, a video update FIFO buffer is provided for buffering video information between the terminal processor and the video memory. The 3-word FIFO buffer is filled during screen trace, and it transfers its contents into the video memory during screen retrace periods.The FIFO buffer permits screen information to appear without flicker. It also permits scrolling of row segment screen information by reading a row segment from the video memory, temporarily storing it, and then writing it into an adjacent row segment. It also permits flexible cursor symbols, cursor blinking of individual display screen areas, and certain data format conversions.

Abstract: In a status-change gathering apparatus wherein status-change data is supplied to a processor from a plurality of inputting devices having a function of detecting status changes in a process or the like, each of the inputting devices is capable of producing an enable signal at a period not greater than the maximum allowed time between a detected status change in a controlled process and the controlling action to be performed by the processor, and of supplying the processor directly with an interrupt signal for requesting data gathering only when the enable signal is "on" and the status change has been detected. Upon receiving an interrupt signal from at least one inputting device, the processor sends a sense signal to all inputting devices, and any inputting device which has generated an interrupt signal places a response signal on a unique line to the processor to identify that inputting device. In this way, sequential scanning of inputting devices to detect changes in status is avoided.

Abstract: In an intelligent video terminal communicating with a central processor, a video memory controller is provided which performs a variety of data transfer operations in response to commands from a terminal processor. The data transfer operations include block reads and block writes, copying an entire screen data line or a portion thereof, scrolling an entire screen line or a portion thereof, filling a screen line or a portion thereof with a desired character, and independently scrolling a row segment within each of multiple independent screen display areas. In addition, the current location of the cursor within each screen display area can be monitored.Many of the data transfer operations are performed by the video memory controller in response to a single terminal processor command, thereby minimizing terminal processor interrupts.

Abstract: A data transformation circuit transforms an input data value into an output value according to a many-to-one mapping scheme by utilizing a hash coding circuit (30) which combines the input data value with a hashing key and a feedback signal. The hashing key is selectively variable and the output of the hash coding circuit is distributed in a selectively variable manner into one of a number of sections of a register (31) to enable the transformation to be modified in a flexible manner.