Abstract: A multiprocessor system having a memory-programmable control of the type having a processor unit, coupling memories and input and output modules for transferring signals to and from a process which is to be controlled. Each processor unit is provided with a subprogram and a data memory which can be accessed directly, and a bus control unit releases access to the common system bus always for only one of the processor units. The access sequence and the access duration of the individual processor units to the common bus, via which the signals run to and from the controlled process, are fixed in a bus assignment matrix. In this manner, simple synchronization of the processor units is achieved. Moreover, guaranteed reaction times with respect to the process are possible.

Abstract: A cartridge programming system is provided for loading selected computer programs into a reprogrammable plug-in cartridge memory. A host computer controls a plurality of remote programming terminals. The terminals contain a library of programs. The consumer can select one and have it loaded into a blank cartridge. The terminal verifies the integrity of the copy and records the transaction. The host can send new programs to the terminals via dial-up telephone lines and can request data on copying-transactions. Various security measures help assure accurate accounting of copies made, thereby assuring authors and their assignees that proper royalties can be billed.

Abstract: A signal address arithmetic circuit is used for performing address arithmetic required for executing such analog signal algorithms as adaptive predicative coding, adaptive bit allocation in predictive coding, adaptive transform coding, etc. The address arithmetic circuit is constructed of two counters, three registers, two selectors, a shift circuit an adder and AND gate circuits. The first selector selects either one of the first counter, the second counter or a first register, and its output is applied to one input terminal of the adder. The second selector selects either one of the second counter or the third register and its output is directly applied to the other input of the adder. The output of the adder and the content of the second register for each bit are applied to the AND gate circuits and its output is set in the third register, the content thereof being used for memory addressing.

Abstract: Information exchange method in a communications controller comprising a central control unit (CCU) associated with a storage that provides a number of parameter/status and data areas equal to the maximum number of interfaces to be managed by the controller. The storage contains a line vector table which indicates the address of each area assigned to each interface. The exchange of the parameter/status information and data on the input/output bus (IO5) uses a minimum number of input/output operations controlled by the program stored in the storage (3).

Abstract: An input/output (I/O) system and method for coupling a host computer to a plurality of peripheral devices in which data destined for peripheral devices is transferred to an output data buffer whose locations are paired with output channel addresses stored in an output device table. A microcomputer performs any processing required on data stored in the output data buffer by reading the address and a function code in the output device table then distributes processed data to an output device block whose locations are addresses of output channels. An input data buffer and input device table similarly arranged, collects and processes input data continuously, which input data buffer can be transferred to the host computer, on command, in a high speed burst.

Abstract: A parallel computer system which has a primary task processor, a second primary task processor, a secondary task processor acting as a backup for the second primary task processor transfers messages by:sending messages from the primary task processor to the second primary processor with the second primary task processor operating on the messages by initially storing a received message in a queue and thereafter reading the message from the queue for processing in accordance with the task associated therewith and accumulating a count of the messages read from its queue; and sending the same messages from the first primary task processor to the secondary task processor which stores the messages in a message queue for possible use if the second primary task processor fails. If a primary task processor fails after processing a given number of messages, the secondary task processor associated therewith starts processing the messages in its queue but after having discarded the first given number of messages.

Abstract: A method of providing efficient on-line and interactive application program utilization of an assortment of devices calling for different screen characteristics. An application programmer writes screen definitions for a particular device to be used. These definitions are stored exterior of the application program and are used to define the quantity, order, and placement of the application program's information on the screen. The application program provides services to generate and process each data element which can be presented. These services are used by a mapping system in conjunction with the screen definition to generate and process a device dependent data stream.

Abstract: In an information processor employing a CMOS circuit comprising a first inverter constructed of CMOS field effect transistors and performing a dynamic operation in response to clock signals, and a second inverter which receives an output from the first inverter and which is also constructed of CMOS field effect transistors, the supply of clock signals to the first inverter is stopped in response to a particular microinstruction. After the supply of clock signals is stopped, the output voltage of the first inverter is clamped to a predetermined value, thus reducing the power dissipation in the dynamic CMOS circuit and also preventing the deterioration of data during the stopping of clock signals.

Abstract: A controller for controlling access to a plurality of records that can be accessed and changed by several independent processors comprises: a plurality of flip-flops corresponding in number to the plurality of records with each flip-flop representing a particular record; a circuit for receiving a programmable control word from any of the processors which identifies multiple records of which access is sought; a circuit for selecting in parallel and logically ANDing output signals from all of those flip-flops which correspond to the identified records; a circuit for sending a signal, if the ANDing operation yields a logical ONE, to the processor which sent the control word signaling that it may access and change the identified records; a circuit for setting in parallel via a single pulse all of those flip-flops which correspond to the identified records if the ANDing operation yields a logical ONE; and a circuit for storing the control word if the ANDing operation yields a logical ZERO.

Abstract: A series/parallel/series shift register memory comprises a substrate on which there are provided storage positions for multivalent data elements. There is provided a redundancy generator for generating one or more redundant code elements on the basis of a group of data elements, said redundant code elements being applied to the series input of the shift register memory later than the associated data elements. The code elements are conducted through parallel-connected storage registers which are shorter than those used for the associated data elements, so that a redundancy reducer receives the redundant code elements from a series output before the associated data elements appear on this series output. The reduction of the storage registers, expressed in periods of the shift drive, can be performed in different ways from a technological point of view.

Abstract: This invention is an apparatus and method created around a specialized micomputer attachable to and addressable to each thermister in an array of thermisters used to measure temperature in the sea. The invention provides a number of options so that the same model of microcomputer can be adapted to several different modes of operation and used to monitor a variety of other sensors that have electrical resistance, voltage or current as outputs. Alternate modes of operation for resistive sensors are presented where a number that fixes the measurement as a fraction of the dynamic range of the variable being measured is determined. The system includes the circuits and memory needed to adapt it to any of a variety of sensors measuring physical quantities.

Abstract: A data processing system comprising multiple processing nodes each containing a processor and a data store. The store holds local data, and also holds copies of shared data required by the node. This reduces conflict between the nodes in accessing the shared data. When one node updates the shared data, it sends an update message to all the other nodes over a transmission link. The processor is then free to continue processing. When the message reaches the other nodes, it updates the other copies of the shared data, so as to ensure consistency. Each node receives messages from the link in the same order, and this defines a unique chronological order for the updates, even though the nodes are asynchronous. A node is temporarily suspended if an update occurs out of this correct chronological order.