Abstract: A digital broadcasting system and a data processing method are disclosed. In an aspect of the present invention, the present invention provides a data processing method including receiving a broadcast signal in which main service data and mobile service data are multiplexed, demodulating the received broadcast signal, outputting demodulation time information of a specific position of a broadcast signal frame, and acquiring reference time information contained in the mobile service data frame, setting the reference time information to a system time clock at a specific time based on the demodulation time information and decoding the mobile service data according to the system time clock.

Abstract: Devices and methods described herein decode a sequence of coded symbols by guessing noise. In various embodiments, noise sequences are ordered, either during system initialization or on a periodic basis. Then, determining a codeword includes iteratively guessing a new noise sequence, removing its effect from received data symbols (e.g. by subtracting or using some other method of operational inversion), and checking whether the resulting data are a codeword using a codebook membership function. This process is deterministic, has bounded complexity, asymptotically achieves channel capacity as in convolutional codes, but has the decoding speed of a block code. In some embodiments, the decoder tests a bounded number of noise sequences, abandoning the search and declaring an erasure after these sequences are exhausted. Abandonment decoding nevertheless approximates maximum likelihood decoding within a tolerable bound and achieves channel capacity when the abandonment threshold is chosen appropriately.

Abstract: Devices and methods described herein decode a sequence of coded symbols by guessing noise. In various embodiments, noise sequences are ordered, either during system initialization or on a periodic basis. Then, determining a codeword includes iteratively guessing a new noise sequence, removing its effect from received data symbols (e.g. by subtracting or using some other method of operational inversion), and checking whether the resulting data are a codeword using a codebook membership function. This process is deterministic, has bounded complexity, asymptotically achieves channel capacity as in convolutional codes, but has the decoding speed of a block code. In some embodiments, the decoder tests a bounded number of noise sequences, abandoning the search and declaring an erasure after these sequences are exhausted. Abandonment decoding nevertheless approximates maximum likelihood decoding within a tolerable bound and achieves channel capacity when the abandonment threshold is chosen appropriately.

Abstract: A method includes receiving, by a first device from a second device, a plurality of encoded messages on a plurality of transmission time intervals (TTIs), where the plurality of encoded messages are forward error correction (FEC) encoded, and where the FEC spans the plurality of encoded messages and decoding the plurality of encoded messages using FEC. The method also includes determining a plurality of decoding status messages in accordance with decoding the plurality of encoded messages and transmitting, by the first device to the second device, the plurality of decoding status messages less often than once every TTI.

Abstract: In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Once Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

Abstract: A data reading device and a data reading method for design-for-testing are provided. The data reading device includes a buffer and a data serialization circuit. The data serialization circuit receives a clock positive edge-triggered signal, a clock negative edge-triggered signal, a trigger mask signal, and test data. The data serialization circuit masks one of the clock positive edge-triggered signal and the clock negative edge-triggered signal according to the trigger mask signal, and provides a part of the test data to an output terminal of the data serialization circuit as an output signal of the data reading device according to the unmasked one of the clock positive edge-triggered signal and the clock negative edge-triggered signal. Thus, a data valid window of the test data can be increased.

Abstract: A method includes detecting an encoded data slice of a set of encoded data slices that requires rebuilding. A storage unit of the DSN includes a local memory and cloud-based alternative memory. The storage unit stores at least one of first and second encoded data slices of the set of encoded data slices in the cloud-based alternative memory. The method further includes determining whether to rebuild the encoded data slice using a full rebuild operation or partial rebuild operation. When determined to rebuild the encoded data slice using the partial rebuild operation, a partial rebuild request is sent to the storage unit. The storage unit then generates partial rebuilding data based on the first and second encoded data slices. The rebuilding module then creates a rebuilt encoded data slice from the partial rebuilding data and other partial rebuilding data from other storage units.

Abstract: A distributed storage network (DSN) stores sets of encoded data slices in sets of storage units. A first storage unit assigned to store an encoded data slice included in a set of encoded data slices transmits a rebuild request associated with the storage error to a second storage unit. The second storage unit generates the rebuilt encoded data slice in response to the rebuild request, and transmits the rebuilt encoded data slice back to the first storage unit, which stores the rebuilt encoded data slice.

Abstract: An embodiment encoder device for encoding an information word c=[c0, c1, . . . , cK-1] having K information bits, ci, includes an encoder for a tail biting convolutional code having a constraint length, L, where K<L?1; the encoder being configured to receive the K information bits; and encode the K information bits so as to provide an encoded code word. An embodiment decoder device for determining an information word c=[c0, c1, . . . , cK-1], having K information bits, ci, includes a decoder for a tail biting convolutional code having a constraint length, L, where K<L?1; the decoder being configured to: receive an input sequence; compute at least one reliability parameter based on the received input sequence; and determine an information word c based on the at least one reliability parameter.

Abstract: Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip.

Abstract: A method for evaluating link or component quality using synthetic forward error correction (FEC) includes generating a bit sequence. The method further includes transmitting the bit sequence over a link or through a component under test without adding FEC to the bit sequence. The method further includes receiving a bit sequence transmitted over the link or through the component. The method further includes determining locations of bit errors in the received bit sequence. The method further includes determining locations of synthetic FEC codeword and symbol boundaries in the received bit sequence for the synthetic FEC algorithm against which link or component quality is being evaluated. The method further includes identifying symbol and codeword errors for the synthetic FEC algorithm based on the locations of bit errors in received bit sequence. The method further includes outputting an indication of link or component quality based on the symbol and codeword errors identified for the synthetic FEC algorithm.

Abstract: Systems and methods for accommodating variable page sizes in solid-state drives using customized error correction are disclosed. In one embodiment, a system is disclosed comprising a NAND Flash storage device comprising a plurality of NAND Flash pages; a NAND FTL configured to convert a LBA of a NAND Flash page to a PBA; a syndrome calculator configured to calculate a syndrome using a LBA and an LBA parity matrix, the LBA associated with a read command issued by a host device; and an ECC decoder configured to: read a codeword located at a PBA associated with the LBA associated with the read command, the codeword including a plurality of user data bits and a plurality of parity bits, confirm that the codeword does not contain an error if the codeword converges with the syndrome, and transmit the user data bits to the host device as a response to the read command.

Abstract: Systems and methods presented herein provide for increasing a contention window of a UE employing a LTE communications operating in a radio frequency (RF) band comprising a conflicting wireless technology. In one embodiment, an eNodeB receives a transport block of data from a user equipment (UE). The transport block includes a cyclic redundancy check (CRC). The eNodeB then determines a checksum of the transport block based on the CRC, fails the checksum, and transmits a non-acknowledgement (NACK) of the transport block to the UE based on the failed checksum. The UE, in response to the NACK, increases a contention window and re-transmits the transport block to the eNodeB.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device processes data usage characteristics associated with a data object that is associated with a user to determine an estimated location of the user. When the estimated location of the user compares unfavorably to the home location of the user, the computing device pre-fetches less than the decode threshold number of EDSs, for each set of encoded data slices (EDSs) that respectively correspond to data segments of a data object, from first storage units (SUs) to second SUs associated with the estimated location of the user.

Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.

Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.

Abstract: Input bits are encoded into codewords that include coded bits. Encoding involves applying a first set of polar encoding matrices GY of prime number dimension Y to the input bits to produce output bits, and applying a second set of polar encoding matrices GZ of prime number dimension Z to the output bits to produce the codeword. One or both of GX and GY could be non-2-by-2. Such kernel design and other aspects of code construction, including reliabilities and selection of sub-channels for code construction, non-CRC-aided error correction, and code shortening and puncturing, are discussed in further detail herein.

Abstract: A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword; performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword; and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword. The controller is configured to read a representation of the inverse bit string from the physical location of the memory. The controller is further configured to designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string.