Abstract: According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.

Abstract: The present disclosure a method of decoding a polar code based on a shared node, the method includes extracting an input node from target data that are data to be decoded, by an extractor, sorting the input node as one of a first node of which the pattern of the frozen bit satisfies a predetermined first reference, a second node of which the pattern of the information bit satisfies a predetermined second reference, and a third node that is not the first node and the second node, by a sorter, calculating at least one codeword candidate and at least one path metric that correspond to the input node in accordance with the sorting result by a calculator, finishing decoding the target data by iterating the extracting, the sorting as one, and the calculating of at least one path metric by a controller.

Abstract: A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Abstract: A method includes storing a superset of data on a data storage medium along with a corresponding superset superparity. The superset of data includes multiple sets of data, and the corresponding superset superparity is calculated based on all of the multiple sets of data. The method also includes updating at least one subset of the superset of data. The subset has a subset superparity. The superset superparity is updated with the subset superparity, and the subset superparity and a location of the subset within the superset are employed to carry out error correction operations.

Abstract: A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.

Abstract: A method includes dispersed storage error encoding, by a computing device of a dispersed storage network (DSN), a plurality of data segments to produce a plurality of sets of encoded data slices. The method further includes obfuscating a first set of encoded data slices of the plurality of sets of encoded data slices using a first obfuscating method to produce a first set of obfuscated encoded data slices. The method further includes obfuscating a second set of encoded data slices of the plurality of sets of encoded data slices using a second obfuscating method to produce a second set of obfuscated encoded data slices. The method further includes outputting the first and second sets of obfuscated encoded data slices for storage.

Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During each LDPC decoding iterative operation in the decoding phase: the check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit is configured to: determine a syndrome weight according to the syndrome from the check-node circuit; obtain a previous codeword from a variable-node memory without obtaining a channel value from a channel-value memory; perform bit-flipping on one or more codeword bits in the previous codeword according to the calculated syndrome weight to generate an updated codeword; and subtract the previous codeword from the updated codeword to obtain the codeword difference.

Abstract: The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.

Abstract: A low density parity check (LDPC) decoding device includes a data generator for generating information with a first precision; a data converter for converting the information into a message with a second precision greater than the first precision; and a decoding processor for performing a low density parity check (LDPC) decoding using the message to generate decoded data.

Abstract: An error-handling method, an associated data storage device and the controller thereof are provided. The error-handling method may include: uploading an error-handling program to a buffer memory equipped with error correction code (ECC) protection capability; in response to at least one error, interrupting execution of a current procedure and activating an interruption service; executing the error-handling program on the buffer memory; disabling a transmission interface circuit; resetting at least one hardware engine and at least one NV memory element; performing cache rearrangement regarding a data cache within the data storage device, and programming rearranged cache data into the NV memory element, to perform data recovery; and through activating a watchdog module and the transmission interface circuit and relinking with a host device, completing soft reset to make the data storage device operate normally again.

Abstract: An embodiment of a semiconductor apparatus may include technology to store a first portion of a code for a tile in a first die of the two or more nonvolatile memory die, store a second portion of the code for the tile in a second die of the two or more nonvolatile memory die, and perform an exclusive-or operation to correct a data error in the tile based on the stored first and second portions of the code. Other embodiments are disclosed and claimed.

Abstract: A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.

Abstract: An apparatus, a system and a method use a class of dynamic switching mechanisms with multiple HARQ block sizes to reduce HARQ retransmission overhead while limiting the increase of HARQ ACK feedback overhead. The apparatus includes a first processing unit configured to estimate an intra-subframe fluctuation level of per-codeblock errors; a second processing unit configured to: map the intra-subframe fluctuation level to a hybrid automatic repeat request (HARQ) block size; determine a HARQ acknowledgement (ACK) format based at least in part on the HARQ block size; indicate the selected HARQ block size to a data transmitter; and generate a HARQ ACK. Per-code block link adaptation can be used to support multiple MCSs for a single user in each subframe with fine time-frequency granularity, with low-bandwidth signaling overhead and without a complete dependency on reference signal (RS) structure.

Abstract: There is provided a method of providing adjusted LLR values of a plurality of bits in a codeword to an LDPC decoder, the plurality of bits representing a plurality of charge states of a plurality of memory cells of a non-volatile memory. The method comprises storing in a non-volatile memory controller associated with the non-volatile memory LLR values of the plurality of bits. The controller then determines a plurality of levels of the charge states represented by the plurality of bits. The controller then generates, by a distribution processor, distributions of a population of the plurality of bits in the codeword at each of the plurality of levels at a first and a second time after the first time. The controller then generates the adjusted LLR values based on a comparison between the first and second distributions, and then decodes the codeword according to the adjusted LLR values.

Abstract: A storage device includes a nonvolatile memory device and a controller. A nonvolatile memory device includes a plurality of memory blocks. Each of the plurality of memory blocks is divided into a plurality of zones and is formed on a substrate. Each of the plurality of zones comprises one or more word lines. A controller performs a reliability verification read operation on a first zone of the plurality of zones of a memory block selected from the plurality of memory blocks if a number of read operations performed on the first zone reaches a first threshold value and performs the reliability verification read operation on a second zone of the plurality of zones of the selected memory block if a number of read operations performed on the second zone reaches a second threshold value.

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write accesses for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Abstract: A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects memory error(s) associated with a plurality of sets of memory devices of sets of storage unit(s) (SU(s)) within the DSN that distributedly store a set of encoded data slices (EDSs). The computing device facilitates detection of EDS error(s) associated with the memory error(s). For a set of memory devices, the computing device establishes a corresponding memory replacement priority level and facilitates replacement of corresponding memory device(s) associated with the EDS error(s) based on the corresponding memory replacement priority level.

Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N?1 pre-set error correction number(s), and N is a positive integer larger than 1.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a number of low density parity check (LDPC) codewords failing a LDPC decoding operation and performing a BCH decoding operation on the codeword.