Abstract: An operation method of a nonvolatile memory device includes receiving control signals and a data signal from external of the nonvolatile memory device, generating debugging information based on the control signals and the data signal, receiving a debugging information request from external of the nonvolatile memory device, and outputting the debugging information in response to the debugging information request.

Abstract: An Ethernet connection method and an Ethernet device thereof are provided. The Ethernet connection method and the Ethernet device can transmit data with Error Correction Code (ECC) even with only one twisted pair or two twisted pairs when the Ethernet wire cannot transmit with the full four twisted pairs.

Abstract: A method and device in user equipment and a base station for wireless communication is disclosed. The base station equipment sequentially generates a first information block including bits in a first sub-information-block and a second sub-information-block, performs first channel coding and transmits a first radio signal. The first bit block includes bits in the first information block, the first bit block is used as an input of the first channel coding, the value of the first sub-information-block is related to the number of padding bits, and the relative position of the first sub-information-block and the second sub-information-block in the first information block is related to the number of bits included in the first information block. The present disclosure utilizes the characteristics of serial decoding of a Polar code, and improves the decoding performance using padding bits as frozen bits through the internal indication of the code block.

Abstract: A testing system is provided. The testing system includes: test equipment and a testing-control apparatus. The test equipment is configured to perform tests on a device under test. The testing-control apparatus is configured to execute a test program to control the test equipment to perform a plurality of first test items in the test program on the device under test. The testing-control apparatus retrieves a test result of each of the first test items from the test equipment, and executes a test-program neural network to analyze the test result of each of the first test items to generate the test program for a next test iteration.

Abstract: A system comprising a computer processor comprising a plurality of registers, a load-store unit configured to load data in at least one of the plurality of registers, and a memory. The memory includes a memory location mapped to a first virtual memory address and a second virtual memory address. Issuance of a load from the memory location via the first virtual memory address causes execution of a side effect. The memory also includes a computer program containing programming instructions that, when executed by the computer processor, performs an operation that includes storing a predetermined data value at the memory location, and testing the memory for errors during load operations.

Abstract: A computer-implemented method enables reconstructing contents of blocks in a storage system having l availability zones (AZs), a set of n storage units in each AZ arranged as columns, and a set of m storage blocks in each storage unit. The storage blocks of n+1 of the storage units are parity blocks, where l?1 of the AZs each include an additional parity block. The method includes using the parity blocks and/or data in the AZs and reconstructing contents of blocks in the storage system having l availability zones (AZs) from a concurrent loss of: one of the AZs, a storage unit together with one storage block in one of the remaining l?1 AZs, and one further storage block in each of the remaining l?2 AZs of the storage system.

Abstract: A message system includes a first node that may send a message to a second node, provide metadata associated with the message, and send the metadata to a database. The database may determine that the message was not received by the second node based upon the metadata and a current time, and direct the first node to resend the message to the second node in response to determining that the message was not received. The first node further may resend the message.

Abstract: A memory device includes an error correction code (ECC) block suitable for performing an ECC operation, and generating a flag signal when an error is detected and corrected through the ECC operation in data read from a memory cell array, and a refresh control block suitable for comparing an active row address with a target address in response to the flag signal, and refreshing data of a neighboring address of the target address based on a comparison result.

Abstract: A method of storing data includes receiving general purpose (GP) data and special Error Tolerant or Streaming (ETS) data, storing the GP data using a data storage method, and storing the ETS data using a different data storage method which affects the access rate, resilience to errors, data integrity, storage density, or storage capacity. The storage medium, which can include a disk drive, flash memory, or holographic memory, is utilized differently depending on the required Quality of Service in aspects including block size, storage of error correction codes, utilization of error correction codes, storage area density, physical format pattern, storage verification, or reaction to failed storage verification. For disk drives these differences include spacing between tracks; overlap between tracks; spiral track formatting; concentric track formatting, and size of blocks, and for flash memories these differences include levels per cell and number of cells.

Abstract: System and techniques for error correction code (ECC) memory security are described herein. A write request that includes data is received. An integrity check value (ICV) is computed for the data. Then, the write request is performed, including writing a representation of the data to a data area in memory and writing the ICV into an ECC area in memory. Here, the data area is addressable by a host and the ECC area corresponds to the data area via hardware of the memory.

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

Abstract: Systems and methods are disclosed for error recovery in a digital data channel. In an error recovery approach when the hardware fails to recover a sector, the sample for that sector can be saved along with a metric measure that indicates the quality of the sample. This process can begin from a first on-the-fly receiving and decoding of data. During each step of error recovery, a retry attempt may either use samples obtained during a new decoding attempt or may use a sample, or a combination of samples, having the best metric from an earlier attempt, or a combination of earlier attempts, to perform the recovery during a current retry recovery attempt.

Abstract: According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.

Abstract: Apparatus and method relates generally to data processing kernel. In such an apparatus, a datapath pipeline is configured to process datasets interlaced with respect to one another for multiple passes through a loop with conditional or data dependent decision points. A queue manager is configured with control circuitry sets to provide an instruction interface to the datapath pipeline. Each of the control circuitry sets includes: a first buffer and a second buffer each configured to buffer tokens for correspondence with the datasets. Each of the control circuitry sets further includes: an arbiter configured to decouple the conditional or data dependent decision points from the datapath pipeline to selectively provide access of the first buffer or the second buffer to the datapath functions. Memory is configured to provide access to and storage of the datasets to the datapath pipeline.

Abstract: A dispersed storage network (DSN) includes multiple storage units. A processing unit included in the DSN issues an access request to one of the storage units, and identifies the storage unit as a failing storage unit based, at least in part, on a rate of growth of a network queue associated with the storage unit. the processing unit then issues an error indicator to a recovery unit for further action.

Abstract: A controller may detect unreliable bits of data, memory cells, or bit lines during an error correction process of a read operation based on an error correction code used to generate parity bits for the data. In some embodiments, the controller may use the error correction code to determine a distribution of unsatisfied checks. Based on the distribution, the controller may detect group(s) of bits that more closely resemble a defective group of bits rather than a non-defective group of bits. Based on the detection, the controller may set reliability metrics to values that indicate low levels or reliability, which in turn may increase the probability of successfully correcting the errors and reduce the amount of work the controller needs to do in order to complete the error correction process.

Abstract: Embodiments of this application provide a method for coding in a wireless communication network. A communication device interleave a first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI); wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence. The devices add d first CRC bits on the first interleaved sequence to obtain a second bit sequence, interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence, and polar encode the second interleaved sequence to obtain the encoded sequence.

Abstract: A system for testing a data storage device includes the data storage device, an electronic device and a computer device. The electronic device includes a host device coupled to the data storage device and communicating with the data storage device via an interface logic. The computer device is coupled to the electronic device and is configured to issue a plurality of commands to test the data storage device in a test procedure. When the electronic device has been successfully started up, the computer device issues a first command to the electronic device to trigger the electronic device to enter a hibernate mode. After waiting for a first predetermined period of time, the computer device issues a second command to the electronic device, so as to wake up the electronic device.