Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.

Abstract: A display configured to detect an error in display data without a parallel-serial conversion circuit is provided. The display includes a display area, a control unit, and a plurality of first CRC circuits. The control unit receives whole display data to control the display area. The whole display data includes a plurality of unit display data and a plurality of CRC data. The plurality of unit display data are each composed of a predetermined count of bits. A count of the plurality of CRC data is identical to the predetermined count of bits. The plurality of first CRC circuits correspond to the respective plurality of CRC data.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive metadata from an application, wherein the meta data indicates one or more processing operations which can accommodate a predetermined level of bit errors in read operations from memory, determine, from the metadata, pixel data for which error correction code bypass is acceptable, and generate one or more error correction code bypass hints for subsequent cache access to the pixel data for which error correction code bypass is acceptable, and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.

Abstract: A decoding method for low-density parity-check (LDPC) code is provided and is configured to decode a communication protocol, which is pending to be tested. The communication protocol includes a code word, and the code word includes a code rate. The decoding method includes: receiving the code word of the communication protocol, which is pending to be tested; determining a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory; moving the parity-check matrix from the dynamic memory to a first memory and saving the code word in a second memory; sequentially transmitting the code word from the second memory to a plurality of check node units to calculate according to the parity-check matrix in the first memory; transmitting the code word verified by the check node units back to the second memory.

Abstract: The present invention discloses a unidirectional bit error correction method for a OTP ROM, comprising: applying error correction encoding to bit information and writing the bit information to the OTP ROM; during power-up initialization, converting hard bit information read out from the OTP ROM to soft bit information; during the power-up initialization, performing error correction decoding through a soft bit decoder. The advantages of the present invention include: utilizing otherwise temporarily idle decoding modules in the chip, without requiring additional hardware resource, while providing stronger error correction capability to the OTP ROM, improving the stability of chip applications, prolonging chip service life, and significantly reducing rejection rate in chip production.

Abstract: In a Boundaryless Control High Availability (“BCHA”) system (e.g., industrial control system) comprising multiple computing resources (or computational engines) running on multiple machines, technology for computing in real time the overall system availability based upon the capabilities/characteristics of the available computing resources, applications to execute and the distribution of the applications across those resources is disclosed. In some embodiments, the disclosed technology can dynamically manage, coordinate recommend certain actions to system operators to maintain availability of the overall system at a desired level. High Availability features may be implemented across a variety of different computing resources distributed across various aspects of a BCHA system and/or computing resources. Two example implementations of BCHA systems described involve an M:N working configuration and M:N+R working configuration.

Abstract: Disclosed is a method of detecting and correcting an error in a 3D mesh model. According to the present disclosure, the method includes: determining at least one mesh on the basis of half-edge information; setting at least one cluster including the at least one mesh, on the basis of normal vector information on the at least one mesh; detecting a flip error of the at least one cluster; and correcting the at least one mesh in the at least one cluster in which the flip error is detected.

Abstract: A computer security method including preventing access by a computer in a first computer network to a resource at a location within the first computer network responsive to the computer accessing a computer-readable document retrieved from a second computer network, wherein a reference to the resource is associated with the computer-readable document.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: Provided herein may be a memory controller and an operating method thereof. The memory controller may include: a read fail control circuit configured to perform, when the read operation fails, an assist read operation of determining optimal read voltages to be used to read the selected memory cells, and determine whether a threshold voltage distribution of the selected memory cells is an abnormal distribution based on read-related information obtained by the read operation and the assist read operation; and an error correction code (ECC) engine configured to perform an ECC decoding operation on hard decision data obtained by reading the selected memory cells using the optimal read voltages based on whether the threshold voltage distribution of the selected memory cells is the abnormal distribution.

Abstract: A method of decoding data stored in non-volatile memory in which each memory cell stores data by adopting one of a plurality of storage states.

Abstract: Disclosed herein is a transceiver for a satellite, where the transceiver includes a receiver, a digital data stream processor and at least one transmitter. The receiver is configured to receive an uplink data stream from a satellite gateway or another satellite where the data stream carries a plurality of data packets. The digital data stream processor is configured to process the uplink data stream, to obtain the plurality of data packets, where at least one of the data packets includes payload data and error correcting data allowing a full error correction of the payload data. The data stream processor is further configured to perform no or only a partial error correction of the payload data of the at least one data packet, to obtain a downlink data stream. The transmitter is configured to transmit the downlink data stream to user terminal or another satellite.

Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.

Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.

Abstract: A method includes generating a plurality of blocks of a block chain wherein the plurality of blocks is associated with components of a storage device. The plurality of blocks is generated by a device other than the storage device when the components are manufactured. The method further includes storing a copy of a ledger associated with the generated blocks on the storage device when the storage device comprises computing power sufficient to generate blocks of a block chain. The method also includes generating additional blocks of the block chain. The additional blocks of the block chain are associated with additional components of the storage device when the additional components are manufactured. The additional blocks are generated independently by the device and by the storage device and wherein respective ledgers are updated.

Abstract: A method and apparatus for encoding low-density parity check codes uses parity check matrices composed of circulant blocks. The apparatus operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput.

Abstract: Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A method and a system for monitoring conditions of offline storage devices is disclosed. Predetermined environmental conditions are monitored to determine whether a storage device should be brought online to perform a data integrity check process. The process receives a triggering event that corresponds with the storage device, powers on the storage devices, selects a page from the storage device, and determines a bit error rate. Once the bit error rate is determined, error-correcting code runs to correct the errors. Any uncorrectable errors are reported, and the storage device is brought back offline.

Abstract: In an example, a storage device includes a plurality of pages, a main page table structure, and an auxiliary page table structure. The main page table structure includes a first data mapping between a logical address of first data and a first physical address pointing to a first data page. Further, the auxiliary page table structure includes a first metadata mapping between a logical address of first metadata and a second physical address pointing to a first metadata page.