Patents Examined by Fritz Alphonse
  • Method and device for testing a chain of flip-flops
    Patent number: 10684326
    Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 16, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Clerc, Gilles Gasiot
  • Concurrent serving of a media stream
    Patent number: 10686853
    Abstract: Online content is served to participant devices using two or more systems. The content served by each system is not the same. Rather, the content streams coming from each system is a partial or lower-quality version of the original high-quality version of the content stream. A single one of the partial data streams can be used by the participant device to output a lower-quality version of the original content stream to the user. Alternately, the received partial content streams can be combined to output, to the user, a high-quality version of the original content stream.
    Type: Grant
    Filed: August 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Danny Levin, Bradford R. Clark, Amer Hassan
  • Payload size ambiguity and false alarm rate reduction for polar codes
    Patent number: 10686469
    Abstract: Size ambiguity and false alarm rate reduction for polar codes. A user equipment (UE) may determine a decoding candidate bit sequence for a polar-encoded codeword having a codeword size based on a decoding hypothesis for control information having a particular bit length of multiple different bit lengths for the codeword size. The UE may calculate an error detection code (EDC) value for a payload portion of the decoding candidate bit sequence using an EDC algorithm, and may initialize an EDC variable state with at least one non-zero bit value. Scrambling or interleaving of bits may also be performed prior to, or after, polar encoding and may depend on the bit length. In examples, information bits may be bit-reversed prior to generating an EDC value. In examples, the encoded bits may include multiple EDC values to assist the UE in performing early termination and to reduce a false alarm rate.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Huang Lou, Jing Jiang, Enoch Shiao-Kuang Lu, Gabi Sarkis, Yang Yang, Hari Sankar
  • Memory controller, memory system including the same, and operation method thereof
    Patent number: 10680656
    Abstract: A memory controller includes a command input unit suitable for receiving a write command, a read command, and a send command, a command counting unit suitable for performing a counting operation in response to the write command to produce a counted data, a first Error Correction Code (ECC) encoding unit suitable for performing a first ECC encoding onto a data that is read from a memory device in response to the read command to produce a first ECC encoded data, a second ECC encoding unit suitable for performing a second ECC encoding onto the counted data in response to the send command to produce a second ECC encoded data, and a data output unit suitable for combining the first ECC encoded data and the second ECC encoded data to output a read data.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Young-Ook Song, Sang-Gu Jo, In-Hwa Jung
  • Memory system with cached memory module operations
    Patent number: 10678719
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Methods and arrangements for managing a retransmission by a device on a random access channel in a wireless communication network
    Patent number: 10673569
    Abstract: Methods and arrangements for managing a retransmission on a Random Access CHannel, “RACH”, in a wireless communication network (100). A device (600; 120) performs (404; 502) the retransmission on the RACH, wherein the retransmission is based on a coverage class associated with the device (600; 120). Basing the retransmission on the coverage class e.g. enables reduction of retransmission collisions when the wireless communication network (100) operates as in Extended Coverage GSM, “EC-GSM”.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Björn Hofström, John Walter Diachina, Nicklas Johansson, Claes-Göran Persson
  • Dynamically partitioning media streams
    Patent number: 10666381
    Abstract: Systems, methods, and software technology for partitioning media streams is disclosed herein. In an implementation, an application partitions an encoded media stream into multiple sub-streams having different code rates relative to each other. The sub-streams may then be transmitted to different wireless access points. A change in a monitored performance of at least one of the wireless access points may drive a modification to the partitioning of the media stream such that the code rates change relative to each other.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 26, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Amer Hassan
  • Converting a data chunk into a ring algebraic structure for fast erasure coding
    Patent number: 10657001
    Abstract: One embodiment provides a method comprising arranging a first data chunk into a ring structure, tagging the first data chunk by appending extra data to the first data chunk, and performing erasure coding on the first data chunk utilizing only exclusive or (XOR) operations.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventor: Zhenxing Han
  • Storage protocol matching device and method
    Patent number: 10650907
    Abstract: Disclosed is a storage test apparatus having a storage protocol matching device including an integrated protocol software unit and an integrated protocol hardware unit, in which, when an insertion of a storage is detected, a protocol configuration that matches a protocol of the storage is automatically set through a protocol switching, thereby enhancing the test efficiency.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 12, 2020
    Assignees: EXICON INDUSTRIAL JOINT RND CENTER, EXICON CO., LTD.
    Inventors: Jong Yun Yun, Soo Il Choi
  • TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs
    Patent number: 10649029
    Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Reconfigurable FEC
    Patent number: 10651874
    Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 12, 2020
    Assignee: INPHI CORPORATION
    Inventor: Volodymyr Shvydun
  • Passive array test structure for cross-point memory characterization
    Patent number: 10643735
    Abstract: An apparatus and method for testing two-terminal memory elements organized as a cross-point memory array. The apparatus allows functional testing of two-terminal memory elements organized as a cross-point memory array, and built in a short flow manufacturing process. The proposed apparatus substantially eliminates the use of any type of additional active or passive switches, selectors, or decoders. A large number of memory elements of various memory types including planar (two dimensional) or three dimensional memory structures can be tested without the need of manufacturing selectors or running the full flow process.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 5, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Tomasz Brozek, Christopher Hess, Rakesh Vallishayee, Meindert Lunenborg, Hendrik Schneider, Yuan Yu, Amit Joag, SiewHoon Ng
  • Method, apparatus and electronic device for read/write speed testing
    Patent number: 10643736
    Abstract: The present invention provides a method for read/write speed testing, comprising: obtaining a test speed of reading data from or writing data to each of a plurality of memories, the plurality of memories including a random access memory and at least one buffer memory associated with the random access memory; and determining an actual speed of reading data from or writing data to the random access memory according to the test speed of reading data from or writing data to the each memory. Embodiments of the present invention further disclose an apparatus for read/write speed testing and electronic device. With the embodiments of the present invention, the read/write speed of the random access memory can be tested more accurately.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 5, 2020
    Assignee: Zhuhai Juntian Electronic Technology Co., Ltd.
    Inventors: Zhenbei Yu, Kun Zhao
  • Memory command interleaving
    Patent number: 10642684
    Abstract: Various embodiments described herein provide for grouping read-modify-writes (RMWs) such that multiple RMW command sequences can be executed (or rearranged in the command queue) in an interleaved manner rather than being executed in order. In particular, various embodiments described herein split the read and write components (commands) of multiple RMW command sequences, group the read components in the command queue to execute consecutively, and group the write components in the command queue to execute consecutively.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: John M. MacLaren, Anne Hughes, Thomas J. Shepherd, Carl Nels Olson
  • Method of controlling error check and correction (ECC) of non-volatile memory device and memory system performing the same
    Patent number: 10635532
    Abstract: A method for controlling error check and correction (ECC) of a non-volatile memory device includes storing write data in a plurality of storing regions. The write data may be generated by performing ECC encoding. Individual ECC decoding may be performed based on each of a plurality of read data read out from the storing regions. Logic operation data may be provided by performing a logic operation of the read data when the individual ECC decoding fails with respect to all of the read data. Combined ECC decoding may be performed based on the logic operation data.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Suk Kim, Sang-In Park, Il-Han Park, Sang-Yong Yoon, Gyu-Seon Rhim, Sung-Woon Choi
  • Storage device, host system, and information processing system
    Patent number: 10635514
    Abstract: A storage device includes a receiving circuit including a correction circuit configured to correct an input signal from a host system based on correction factors and output the corrected input signal as an output signal containing a data value that is to be stored in the storage device, an interface controller configured to adjust the correction factors based on a difference value generated by the correction circuit using the output signal, and a transmission circuit configured to transmit the correction factors to the host system.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayoshi Sato, Ichirou Hara
  • Memory controller assisted address mapping
    Patent number: 10635599
    Abstract: An apparatus includes a storage controller, a non-volatile memory die comprising a set of memory elements and a memory die controller associated with the non-volatile memory die. The memory die controller is configured to identify a portion of the non-volatile memory die for mapping logical addresses, read a header of a sub-portion of the identified portion, for a logical address, map a physical address corresponding to the logical address of the sub-portion to a physical-to-logical mapping and transmit the physical-to-logical mapping to the storage controller.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Yacov Duzly, Yan Li, Idan Alrod
  • Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and 64-symbol mapping, and bit interleaving method using same
    Patent number: 10623023
    Abstract: A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 14, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Method of arrangement of an algorithm in cyclic redundancy check
    Patent number: 10623018
    Abstract: A method of arrangement of an algorithm to calculate cyclic redundancy check (CRC) independent of the length of a polynomial generator and data stream which can be realized in digital implementation with a calculation latency of once clock cycle. The method allows a sequence of information and the corresponding polynomial generator be arranged into a transformation table.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: April 14, 2020
    Assignee: AKRIBIS SYSTEMS PTE LTD
    Inventors: Shee Jia Chin, Yong Min Kong
  • Global error recovery system
    Patent number: 10613930
    Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Hashimoto, Hironori Uchikawa