Abstract: Provided herein may be an error correction circuit, and a memory controller and a memory system. The error correction circuit may include an encoder configured to generate a codeword comprising a message part, a first parity part, and a second parity part, and a decoder configured to perform error correction decoding using read values corresponding to at least a portion of the codeword, wherein, the decoder is configured to perform error correction decoding based on a first or a second error correction ability such that error correction decoding using the first error correction ability is performed using partial read values corresponding to a partial codeword including the message part and the first parity part, and error correction decoding using the second error correction ability is performed using read values corresponding to the entire codeword, and wherein the second error correction ability is greater than the first error correction ability.

Abstract: An apparatus includes a first function module providing a master signal, a second function module providing a comparison signal, and safety logic. The safety logic includes a toggle signal generator having a comparator providing a comparison result in response to the master signal and the comparison signal, a feedback path generating a first toggle signal in response to the comparison result and providing a feedback signal to the comparator, and a first multiple input gate generating a second toggle signal in response to the comparison result. The safety logic also includes a toggle signal monitor providing a final fault search signal in response to the first toggle signal and the second toggle signal.

Abstract: A function verification method for a boundary scan test controller is disclosed. In the method, the configuration positions of input/output connectors on a test board correspond to configuration positions of to-be-verified connectors on a boundary scan test controller, so that when the test board is stacked and positioned on the boundary scan test controller, the input/output connectors can be electrically connected to the to-be-verified connectors corresponding thereto, respectively. After being electrically connected to the boundary scan test controller via a USB port, the test control host creates a test script according to information of the test board and all operations of the to-be-verified connectors, and then execute a test program in the to-be-verified connectors according to the test script, and generates a test report, and determines whether the boundary scan test controller meets shipment or production requirement according to the test report.

Abstract: An apparatus includes a first function module providing a master signal, a second function module providing a comparison signal, and safety logic. The safety logic includes a toggle signal generator having a comparator providing a comparison result in response to the master signal and the comparison signal, a feedback path generating a first toggle signal in response to the comparison result and providing a feedback signal to the comparator, and a first multiple input gate generating a second toggle signal in response to the comparison result. The safety logic also includes a toggle signal monitor providing a final fault search signal in response to the first toggle signal and the second toggle signal.

Abstract: A transmission method includes performing LDPC coding on a basis of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 3/16, and performing group-wise interleaving in which the LDPC code is interleaved in units of bit groups of 360 bits. The transmission method further includes mapping the LDPC code to one of 16 signal points of uniform constellation (UC) in 16QAM on a 4-bit basis. In the group wise interleaving, an (i+1)th bit group from a head of the LDPC code is set as a bit group i, and a sequence of bit groups 0 to 191 of the 69120-bit LDPC code is interleaved into a sequence of bit groups.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.

Abstract: A method begins when a read expansion condition is met for a set of encoded data slices stored in a set of storage units of a first DSN. The method continues with determining whether a difference between a pillar width number and a read threshold (RT) number is greater than or equal to the RT number. When no, the method continues with retrieving an expansion number of encoded data slices from the set of storage units and sending them to storage units of a second DSN for storage. The method continues by receiving a plurality of read requests for the set of encoded data slices, sending a first group of read requests to a RT number of storage units of the first DSN and sending a second group of requests to a second subset of storage units of the first DSN and to the storage units of the second DSN.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.

Abstract: A method begins by obtaining, for a set of data access requests to a set of storage units of a dispersed storage network, a storage-revision indicator from each of at least some storage units of the set of storage units, where the set of data access requests is regarding a data access transaction involving a set of encoded data slices. The method continues by generating an anticipated storage-revision indicator for the data access transaction based on a current revision level of the set of encoded data slices and a data access type of the data access transaction. The method continues by comparing the anticipated storage-revision indicator with the storage-revision indicators received from the at least some storage units. When a threshold number of the storage-revision indicators received from the at least some storage units substantially match the anticipated storage-revision indicator, the method continues by executing the data access transaction.

Abstract: A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.

Abstract: An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.

Abstract: A system includes a host configured to communicate with a device under test. The host is configured to write test data to the device under test. An optimization engine is configured to optimize a plurality of parameters associated with a magnetic recording channel associated with the device under test. The optimization engine is configured to select a first set of parameters for the plurality of parameters and the host is configured to set the magnetic recording channel based on the first set of parameters. The host then measures the performance of the magnetic recording channel based on the first set of parameters. Based on the measured performance, the optimization engine then selects new parameter values for the plurality of parameters. Until the measured performance is within an acceptable threshold, the optimization engine will iteratively update the plurality of parameters based on the measured performance.

Abstract: A method for transmitting a broadcast signal in a digital transmitter, includes generating at least one component for at least one service, wherein the at least one component is carried based on a ROUTE protocol; generating at least one signaling data, wherein the at least one signaling data includes broadcast stream ID for identifying one or more broadcast streams comprising the at least one service, first capability information for presenting all services in the at least signaling data, service ID for identifying the at least one service, and second capability information for presenting a specific service related to the service ID information; and transmitting the broadcast signal comprising the at least one signaling data and the at least one component, wherein the at least one component is carried via at least one physical layer pipe.

Abstract: A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device processes data usage characteristics associated with a data object that is associated with a user to determine an estimated location of the user. When the estimated location of the user compares unfavorably to the home location of the user, the computing device pre-fetches less than the decode threshold number of EDSs, for each set of encoded data slices (EDSs) that respectively correspond to data segments of a data object, from first storage units (SUs) to second SUs associated with the estimated location of the user.

Abstract: Technologies for built-in self-testing of a memory array using error detection and correction code knowledge include identifying data errors between pseudo random data written to the memory array and the data read back from the memory array and ignoring those data errors determined to be correctable. The data errors may be determined to be correctable if an error corrector circuit can correct those errors or if the number of errors per memory chuck is less than a number of errors correctable by the error correct circuit.

Abstract: The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

Abstract: A method for execution by a dispersed storage and task (DST) execution unit identifying a failing memory device based on memory device diagnostic data. A cloning task is executed by designating memory of a replacement memory device to store encoded slices stored in the failing memory device, where the cloning task is executed over a cloning duration time period. A write request is received via a network at a receiving time during the cloning duration time period that includes a new encoded slice, and the new encoded slice is assigned to a temporary memory device for storage based on an identifier of the new encoded. The new encoded slice is transferred from the temporary memory device to the replacement memory device in response to an elapsing of the cloning duration time period corresponding to completion of the execution of the cloning task.

Abstract: A first error-detecting code (EDC) is computed based on a first segment of a block of information that is to be encoded, and a second EDC is computed based on at least a second segment of the block of information. The first EDC is masked with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC. The first masking segment and the second masking segment are associated with a target receiver of the block of information. A codeword is generated based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC. This type of coding could be useful to support early termination of blind detection at a decoder, for example.