Abstract: The present invention discloses an organic light-emitting diode display device. More particularly, the present invention relates to the structure of an organic light-emitting diode display device for suppressing a vertical crosstalk phenomenon in the organic light-emitting diode display device having an internal compensation structure for threshold voltage variations in driving transistors. According to an embodiment of the present invention, a shield electrode may be formed using the same metal layer as that of scan lines or data lines, thereby providing an organic light-emitting diode display device in which the effect of coupling between the gate electrode of driving thin-film transistors and the data lines is minimized.

Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.

Abstract: A MEMS device with a first electrode, a second electrode and a third electrode is disclosed. These electrodes are disposed on a substrate in such a manner that (1) a pointing direction of the first electrode is in parallel with a normal direction of the substrate, (2) a pointing direction of the third electrode is perpendicular to the pointing direction of the first electrode, (3) the second electrode includes a sensing portion and a stationary portion, (4) the first electrode and the sensing portion are configured to define a sensing capacitor, and (5) the third electrode and the stationary portion are configured to define a reference capacitor. This arrangement facilitates the MEMS device such as a differential pressure sensor, differential barometer, differential microphone and decoupling capacitor to be miniaturized.

Abstract: The invention describes a multi-device OLED (1) comprising a device layer stack (100) comprising a bottom electrode (11), a top electrode (14), at least one inter electrode (13) and plurality of active layers (120, 121), wherein the bottom electrode (11) is applied to a substrate (10), and each active layer (120, 121) is enclosed between two electrodes (11, 13, 14); a current distribution means (500) comprising a current distribution layer (51, 53, 54) for each electrode (11, 13, 14) of the device layer stack (100); a plurality of openings (110, 130) extending from the top electrode (14) into the device layer stack (100), wherein each opening (110, 130) exposes a contact region (111, 131) of an electrode (11, 13); and a plurality of electrical connectors (41, 42), wherein an electrical connector (41, 42) extends into an opening (110, 130) to electrically connect the electrode (11, 13) exposed by that opening (110, 130) to the current distribution layer (53, 54) for that electrode (11, 13).

Abstract: A thin film transistor substrate with an adhesive strength between a semiconductor layer and a source electrode, and between a semiconductor layer and a drain electrode; and an LCD device using the thin film transistor substrate. The thin film transistor substrate includes a substrate, a gate electrode on the substrate, a gate insulating film on the gate electrode, an active layer on the gate insulating film, an ohmic contact layer on the active layer, a barrier layer on the ohmic contact layer. The barrier layer is formed of a material layer containing Ge. A source electrode and a drain electrode are on the barrier layer. The source and drain electrodes are provided at a predetermined interval from each other.

Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.

Abstract: A light-emitting device comprises a first semiconductor layer; and a transparent conductive oxide layer comprising a diffusion region having a first metal material and a non-diffusion region devoid of the first metal material, wherein the non-diffusion region is closer to the first semiconductor layer than the diffusion region.

Abstract: Various embodiments of a portable cooking apparatus are disclosed. For example, in one embodiment, a portable cooking system is provided comprising a cooking plate having a continuous cooking surface, a heating element assembly disposed beneath the cooking surface, a temperature controller for varying the temperature of the cooking surface, and a base that supports the cooking plate on an underlying surface. The base comprises an integrally formed drip pan located beneath the cooking surface, the integrally formed drip pan comprising a recessed portion formed in a top surface of the base.

Abstract: An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.

Abstract: A MEMS device includes a dual membrane, an electrode, and an interconnecting structure. The dual membrane has a top membrane and a bottom membrane. The bottom membrane is positioned between the top membrane and the electrode and the interconnecting structure defines a spacing between the top membrane and the bottom membrane.

Abstract: A device includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. The device further includes a first node and a second node, and an Electro-Static Discharge (ESD) device coupled between the first node and the second node. The ESD device includes a semiconductor fin adjacent to and over a top surface of the insulation region. The ESD device is configured to, in response to an ESD transient on the first node, conduct a current from the first node to the second node.

Abstract: A MEMS capacitive pressure sensor is provided. The MEMS capacitive pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The capacitive pressure sensor also includes a second dielectric layer having a step surface profile formed on the first dielectric layer, and a first electrode layer having a step surface profile formed on the second dielectric layer. Further, the MEMS capacitive pressure sensor includes an insulation layer formed on the first electrode layer, and a second electrode layer having a step surface profile with a portion formed on the insulation layer in the peripheral region and the rest suspended over the first electrode layer in the device region. Further, the MEMS capacitive pressure sensor also includes a chamber having a step surface profile formed between the first electrode layer and the second electrode layer.

Abstract: An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract: A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.

Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract: Embodiments of the present invention provide an organic light emitting diode display panel and a method for manufacturing the same. The manufacturing method comprises: coating a photoresist layer on a transparent substrate with an active array formed; performing exposure on the photoresist layer from one side of the transparent substrate opposed to the photoresist layer, where the scan lines and the at least one kind of lines are used as a mask to prevent exposure of the corresponding photoresist, so that a photoresist remaining region is formed by the photoresist layer; conducting a development treatment on the photoresist layer, so that the photoresist outside the photoresist remaining region is removed and the photoresist in the photoresist remaining region is retained to form the pixel defining layer. The embodiments of the invention may simplify the fabricating flow of the display panel, reduce production costs of the display panel, and increase yield of the display panel.

Abstract: An array substrate for a narrow bezel type liquid crystal display device and method of manufacturing the same are provided. The array substrate includes: gate lines (GLs) on a substrate, the substrate including a display area and first to fourth non-display areas at respective sides, pixel regions, a gate insulating layer (GIL) on the GLs, a plurality of data lines on the GIL and crossing the GLs, a plurality of gate auxiliary lines parallel to the data lines and connected to respective GLs, an auxiliary line in the third non-display area with a first layer under the GIL and a second layer on the GIL, the first layer contacting the second layer through a first auxiliary contact hole in the GIL, a thin film transistor in each pixel region and connected to the GLs and data lines, and a pixel electrode connected to each thin film transistor.

Abstract: A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration.