Abstract: A computer-aided software development system includes programs to implement edit, compile, link and run sequences, all from memory, at very high speed. The compiler operates on an incremental basis, line-by-line, so if only one line is changed in an edit session, then only that line need be recompiled if no other code is affected. Scanning is done incrementally, and the resulting token list saved in memory to be used again where no changes are made. All of the linking tables are saved in memory so there is no need to generate link tables for increments of code where no changes in links are needed. The parser is able to skip lines or blocks of lines of source code which haven't been changed; for this purpose, each line of source text in the editor has a change-tag to indicate whether this line has been changed, and from this change-tag information a descriptor table is built having a clean-lines indication for each line of source code, indicating how many clean lines follow the present line.

Abstract: The decoding of certain instructions cause an instruction unit of a production line data processing system to stall. Instructions still in the production line are executed, but no new instructions are sent into the production line until the instruction that caused the stall condition is executed. The execution of the instruction that caused the stall is completed by an execution unit taking over control of an address unit.

Abstract: A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths for transmit/receive. An adapter couples a CPU or the like at a node to the serial link. The adapter includes a packet memory for temporarily storing transmit packets and receive packets, along with a port processor for executing the protocol. Packets of data are transferred between the system bus of the CPU and the packet memory of a pair of data movers, one for read and one for write. The packet memory is accessed upon demand by the serial link, the port processor and the data movers, using interleaved cycles. To accommodate this access upon demand without request/grant cycles, parking registers are provided to store read or write data until a later cycle, and the data rate on the packet memory port is high enough to allow ample time for simultaneous use of both channels as well as packet processing and moving to and from the CPU.

Abstract: A packet data communication system employs a congestion avoidance method in which each node measures the round-trip delay occurring when it sends data to a destination and receives an acknowledgement. This delay is measured for different load levels, and a comparison of these delays is used to determine whether to increase or decrease the load level. The load level can be adjusted by adjusting the window size (number of packets sent in to the network) or by adjusting the packet rate (packets per unit time). The objective is operation at the knee in the throughput vs. traffic curve, so that the data throughput is high and the round trip delay is low. Control is accomplished at each node individually, without intervention by the router or server, so system overhead is not increased.

Abstract: A method for establishing and maintaining virtual chains in a distributed computer network during session initiation. In transmitting a session initiation request from an originating network node to a destination network node, a locate chain is established along the path taken with control block resources dedicated to the chain at each intermediate node. By sending a reply with the discard indicator set, the resources at the intermediate nodes become immediately available and only the network node servers maintain knowledge of the pending session initiation and the route selected.

Abstract: A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths for transmit/receive. An adapter couples a CPU or the like at a node to the serial link. The adapter includes a packet memory for temporarily storing transmit packets and receive packets, along with a port processor for executing the protocol. The packet memory includes two zones in which the received packets are stored interchangably. Packets of data are transferred between the system bus of the CPU and the packet memory by a pair of data movers, one for read and one for write. The packet memory is accessed upon demand by the serial link, the port processor and the data movers, using interleaved cycles. The order of buffering the received packets in the two zones is recorded in a file or silo, and when the packets are transferred to the CPU the packets are accessed by referring to this silo so the order of receipt is maintained.

Abstract: A computer-aided software development system includes programs to implement edit, compile, link and run sequences, all from memory, at very high speed. The compiler operates on an incremental basis, line-by-line, so if only one line is changed in an edit session, then only that line need be recompiled if no other code is affected. Scanning is done incrementally, and the resulting token list saved in memory to be used again where no changes are made. All of the linking tables are saved in memory so there is no need to generate link tables for increments of code where no changes in links are needed. The parser is able to skip lines or blocks of lines of source code which haven't been changed; for this purpose, each line of source text in the editor has a change-tag to indicate whether this line has been changed, and from this change-tag information a clean-lines table is built having a clean-lines indication for each line of source code, indicating how many clean lines follow the present line.

Abstract: In a multiprocessor system (FIG. 1), the processors (10-12) are interconnected by a non-blocking communication medium such as a crossbar switch (19). Each processor is connected to a dedicated port circuit (18) at the switch by an optical link (16). Each port circuit is connected to the crossbar switch by an electrical link (20). The port circuits are interconnected by a contention medium (14). A port circuit sends an access request by its connected processor to the destination processor over the contention medium. Circuitry (205) at each port circuit receives requests, for access to the connected processor, prioritizes conflicting requests, and grants them sequentially. The circuitry interleaves grants of access to the connected processor with grants of outgoing access requests made by the connected processor. The circuitry grants an access request by causing the crossbar switch to establish the corresponding connection.

Abstract: A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

Abstract: A parallel computer comprised of a plurality of identical processors, each processor having control and data inputs and outputs for communication with the host computers and separate interprocessor inputs and outputs for communication between the processors. The processors are permanently interconnected through interprocessor communications routers into a first, single n-cube array for purposes of interprocessor communication. The data and control inputs and outputs of the processors are separately connected in parallel to the host computers through a resource allocation means to divide the first, single n-cube array of processors into a multiplicity of smaller second arrays controlled by selected ones of the host computers.

Abstract: In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

Abstract: A data control system includes an external memory unit for storing data, a volatile memory for storing at-least-once accessed data from the external memory unit, a nonvolatile memory for storing frequently-accessed pieces of data among the data stored in the volatile memory, and a memory control unit for controlling the external memory unit and the nonvolatile memory. The frequently-accessed data is stored in the nonvolatile memory, so that when the system is powered down, the nonvolatile memory does not lose the frequently-accessed data. When the power is on, the frequently-accessed data can be again accessed rapidly.

Abstract: A computer-aided software development system includes programs to implement edit, compile, link and run sequences, all from memory, at very high speed. The compiler operates on an incremental basis, line-by-line, so if only one line is changed in an edit session, then only that line need be recompiled if no other code is affected. Scanning is done incrementally, generating a sequential token list which is saved in memory to be used again where no changes are made; increments of the sequential token list are reused when no changes have been made in the increments and related statements. All of the linking tables are also saved in memory so there is no need to generate link tables for increments of code where no changes in links are needed. The parser is able to skip lines or blocks of lines of source code which haven't been changed.

Abstract: A document retrieval system employs a keyword connection table which contains relation information of keyword connections respectively coupling two arbitrary keywords which are used for retrieving registered documents. The relation information at least includes a relation name and a relationship describing the relation between the two arbitrary keywords. The relation information may dynamically change depending on a frequency of use of the keywords, that is, by a learning function.

Abstract: A microprocessor chip including a ROM portion for storing a microprogram, an execution unit portion for executing an arithmetic operation and random logic circuits disposed between the ROM portion and the execution unit portion. Two-level metal lines technology is used for supplying power for grounding and for providing input/output interconnect lines for the random logic circuits.

Abstract: A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruction. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.

Abstract: Cache memory having pseudo virtual addressing, in which the addressing is performed by using the "offset" field of a current address and a physical address field of an address previously used and stored in a first register, and where, for each logical current address a comparison is made between the logical page addresses of the current address and that of the last used physical address which is stored in a second register. Along with the requested information the cache memory outputs, if available, the effective physical page address of the information, which is compared with the physical page address used for addressing and stored in the first register. In this way, the addressing is performed by physical addresses but without need to wait for translation of a virtual/logical address into a physical address.

Abstract: The multiplexing character processor of the present invention multiplexes data characters to and from a plurality of communication lines to a Central Processing Unit by bit slicing. Input data present on the plurality of communication lines is sampled at a rate which is at least 16 times the data bit rate and is formulated as a serial data bit stream. Each sample corresponds to a time slice which slice is allocated to a given communication line under the control of a scan list. A high data rate communication line can be placed on the scan list more than once to insure accurate data reproduction. Character assembly and disassembly is performed in an arithmetic logic unit (ALU) under program control, to provide the flexibility to support various communication link protocols. The input data on each communication line may have a different protocol. Synchronization of the serial data bits to the communication lines is performed by a data bit synchronizer DBS.

Abstract: A resumeable batch query object class provides a link between a first dialog for obtaining information regarding a query to be performed by an object oriented database management system, a second dialog for manipulating the results of the query, and the stream which includes the query results. The resumeable batch query attributes include identifiers of the second dialog and the stream, and a method to run the query. The resumable batch query is used by the object oriented database management system to allow a second dialog to manipulate results of a batch or background query in the same manner as results of a foreground or interactive query. Time consuming queries may thereby be processed in background mode in a manner which is transparent to the second dialog.

Abstract: An external clock unit for use with a DEC MICROVAX model 31 computer includes a first crystal oscillator for generating a clock signal of about 44 MHZ, a second crystal oscillator for generating a clock signal of about 63 MHZ, a 2 to 1 multiplexor for receiving 44 MHZ clock signal and the 63 MHZ clock signal and outputting one of clock signals, a first switch for selecting which of the two clock signals is to be outputted by the 2 to 1 multiplexor, a second switch for selecting which one of two logic signals is to be outputted by a system identification code generator in the computer and a power supply for providing power to the device. In use, the external clock unit is connected to jumper pins on the processor clock signal line and the system identification code generator.