Abstract: A least-recently-used (LRU) circuit determines a replaceable term needed for storing data newly loaded from cache memory for example. The circuit comprises a recently-used information storing means relating to the top priority order or the subordinative order among plural terms, and a least-recently-used determining means for determining which is the top priority term or the subordinative term in accordance with information stored in the recently-used information storing means. High speed processing is thus possible by simplified logical construction. Also, the circuit is provided with control means which directly or indirectly select the predetermined replaceable term, in situations where the determining means cannot properly determine the top-priority replaceable term. Therefore, even when the top-priority replaceable term is selected directly or indirectly, the cache memory can be securely prevented from discontinuing its own functional operation.

Abstract: A semiconductor chip for processing or storing information and a system comprising a plurality of semiconductor chips for processing or storing information. In one form of the invention each chip includes clock input and output circuitry for receiving and transmitting signals of a first frequency and transmission circuitry for receiving and transmitting data. The transmission circuitry is capable of sampling the data at a second clock frequency which is less than the first clock frequency. Circuit components are coupled to the clock circuitry and transmission circuitry for processing the data. In another form of the invention a semiconductor chip comprising clock input and output circuitry, transmission circuitry and circuit components for processing data further includes input circuitry for selecting a variable delay between the time data is received onto the chip and transmitted from the chipIn a preferred embodiment of the invention the semiconductor chip includes a memory array for storing data.

Abstract: A method for dispatching work requests in a data storage hierarchy in which directory data is promoted in variable length spans, the use of which are maximized even for work requests entering the work request queue after the span is chosen, is disclosed. A queue of work requests is initially scanned to determine if any requests therein require access to directory data stored in secondary storage within a prescribed proximity of that required by the next request to be dispatched. If such other work requests exist, then directory data in addition to that required by the next request to be dispatched is also promoted. To minimize seek time and rotational latency, the additional data is promoted from secondary storage in a single device I/O cycle. The additional data is chosen by adjusting the outer limits of the span as each work request in queue is scanned. After the actual promotion of the span of data, the existing work request is completed.

Abstract: A computer interconnect coupler has channel transmitters and channel receivers and logic circuitry for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgment responsive to the incoming message.

Abstract: A control method for processing elements (PE) in a parallel processing system, such as an array processor, in which data processing is carried out with data transfer between the PEs, and wherein the data transfer between the PEs is performed simultaneously with the data operations in the PEs to improve the processing speed of the parallel processing system. Three buffer memories are respectively connected to a data input path from one data procesing apparatus, a data output path to another data processing apparatus, and data paths for transmitting data from or to the data operation unit in the data processing apparatus itself having these three buffer memories.

Abstract: The present invention provides to the software application the verification and license check out functions which are normally performed by a license server of a network software license system. The encrypted license information is contained in a license token, and is sorted in the database controlled by the license server. In contrast to the prior art where the license server either grants or denies the request after verifying the user's credentials, the license server in the preferred embodiment of the present invention finds the correct license token for the software application and transmits the license token to the licensing library. In application specific license access module attached to the application decodes the licensing token. Routines in the licensing library coupled to the software application verify the license information before checking out the license and updating the license token.

Abstract: An object based operating system for a multitasking computer system provides objects which represent the architecture or interrelationships of the system's resources. Access to certain objects is required in order to use corresponding resources in the system. All objects have a consistent data structure, and a consistent method of defining the operations which apply to each type of object. As a result, it is relatively easy to add new types of system objects to the operating system. The object based operating system supports multiple levels of visibility, allowing objects to be operated on only by processes with the object's range of visibility. This allows objects to be made private to a process, shared by all processes within a job, or visible to all processes within the system. An object or an entire set of objects can be moved to a higher visibility level when objects need to be shared.

Abstract: In an operating system generation method of a computer, a symbolic name is converted into an identification code, which is further converted into an address. This enables an inter-reference operation to be achieved between a kernel and input/output device drivers, thereby independently generating the input/output device drivers and the kernel. As a result, depending on the hardware configuration of the user system, input/output device drivers can be incorporated into the operating system.

Abstract: A distributed office automation system includes workstations and support stations which are interconnected via a network and which make use of the functionality of one another by subcontracting tasks. Various function modules are available in the system for numerous tasks and the system provides a distributed organization structure in which it is always clear what function module is required to perform a specifc task. Each of the stations is provided with a coordination unit which is continually aware of the state of the total system and which designates the required function module.

Abstract: A computer system especially for solution of real time inference problems is disclosed. The system includes a systolic cellular processor which provides predictable and responsive real time operation and fine grain programmability. The system comprises a plurality of separate processor cells each having its own local memory, the cells running simultaneously and operative to execute their respective program instructions. A global memory is coupled via a global bus to the processor cells and provides data to the cells and stores data from the cells. The bus provides effectively simultaneous access of all cells to the global memory. A further feature of the system is a novel parallel programming language using English syntax and which provides synchronous and predictable binding of code to each cell. A graphic work station is provided as a user interface to provide visual access to each cell or to cell groups for ease of control.

Abstract: An apparatus and method for decreasing the memory requirements of BIOS in a personal computer system includes storing a first portion of BIOS in memory and a second portion on a direct storage access device. The personal computer system comprises a system processor, a random access main memory, a read only memory, and at least one direct access storage device. The first portion of BIOS only includes routines for initializing the system and the direct access storage device to read in a master boot record into the system from the direct access storage device. The master boot record includes a data segment and an executable code segment. The first BIOS portion vectors the system processor to execute the executable code segment of the master boot record. The executable code segment loads in the remaining BIOS portion from the direct access storage device into random access memory superseding the first BIOS portion.

Abstract: A latch circuit receiving the system reset signal and the error signal from a coprocessor provides an output indicating the presence of the coprocessor. The latch circuit provides the output for computer systems which cannot connect the coprocessor error signal to a coprocessor error input on the processor.

Abstract: A virtual lookaside faclity is provided for maintaining named data objects in class-related data spaces in virtual storage, readily retrievable by user programs. A search order is associated with each user, specifying an ordered list of "major names" which are, in effect, sequentially searched for a specified "minor name", or data object, to obtain a virtual storage copy of that data object. As data objects are placed into a virtual cache, existence information, implicit in the naming structure, is captured and saved. This information is relied on later in retrieving objects from the cache. The data isolation provided by maintaining class data and control blocks in individual data spaces is exploited to prevent failures relating to one class of objects from affecting the others, and to handle latent program users, following failures, effectively.An LRU-like trimming technique is used to remove less useful objects from the cache when cache space is fully utilized.

Abstract: A method for efficient generation of complied code is presented. In order to gain significant performance advantage with a minimum of code expansion, out-of-line code sequences are used. An out-of-line code sequence is a series of instructions that are invoked by a simplified calling mechanism in which almost no state-saving is required. Additionally, out-of-line code sequences is designed so that a single copy can exist on a system and all processes running on that system can access it. A series of out-of-line code sequences can be generated, each member of the series being tailored to a particular combination of compile-time information.

Abstract: A store-in cache memory system for a multiprocessor computer system has a status entry in the cache directory which is RO (read-only) when a line of data is read-only, and thus accessible by all processors on the system, or EX (exclusive) when the line accessible for reading or writing but only by one processor. In addition, each directory has an entry, CH, which is set when data in the line is changed. The cache memory system includes two additional statuses, TEX, or temporary exclusive, and TRO, or temporary read-only. When a data fetch instruction results in a cache-miss, and a line containing the requested data is found in a remote cache with an EX status and with its CH bit set, the line is copied to the requesting cache and assigned a status of TEX. The line of data in the remote cache receives a status of TRO. If a store operation for the data occurs within a short time frame, the status in the requesting cache changes to EX and the line in the remote cache is invalidated.

Abstract: Sequentially scanned digital input signals are applied to the controller to derive output signals which are formed of the sum of scanned values of the signals weighted with selected coefficients. The weighting with the coefficients is carried out by use of coefficients stored in a table, for example a read-only memory (3, 16); the sum of the respectively weighted signals is then formed in a sequential adder (4, 5; 23, 26, 24, 25). Multiplex operation of respective signals, associated with selected coefficient addresses, can be obtained.

Abstract: A multi-station communication bus system allows for the use of several master stations by way of an arbitration organization. A message contains a master address which is subjected to an arbitration operation, a slave address with space for a slave address acknowledge bit, a control signal with space for a control acknowledge bit, and one or more data bytes. For each data byte an indication of the "last" byte is also transmitted and space is reserved for a data acknowledge bit. When a data acknowledge bit is not correctly received, the data byte in question is repeated until at the most the maximum frame length is reached. The remainder of a message is then placed in a next frame. If an address or control acknowledge bit is not correctly received, the relevant frame is terminated. In case of a plurality of bytes in a message, the first frame thereof has a lock control signal that is activated upon communication of at least one data byte.

Abstract: A system for processing data matrices such as images and spatially related data includes a plurality of neighborhood processing units connected in a linear chain with direct data communication links between adjacent processing units. A sequence of instructions are sent to the processing units by a single controller, where all neighborhood processing units in the system receive the same instruction at any given cycle in the instruction sequence. The width of the data matrix array is the same as a number of processors, so that there is one processor per column in the data matrix. The memory associated with each processor is external and large enough to hold the entire image or data matrix. The processors are able to operate arithmetically in a serial or parallel mode, where an efficient means is provided to transpose 8.times.8 bit submatrices between the two modes. An indirect addressing means is provided which operates on byte-wide memories external to the processing unit.

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

Abstract: An interrupt is provided to a signal processor having a non-maskable interrupt input, in response to the detection of a request for transfer to backup software. The signal processor provides a transfer signal to a transfer mechanism only after completion of the present machine cycle. Transfer to the backup software is initiated by the transfer mechanism only upon reception of the transfer signal.