Abstract: An electronic postal meter has an accounting unit with redundant nonvolatile random access memories controlled by a microprocessor system. The redundant random access memories have separate groups of address and data lines to minimize identical errors in data stored therein. The data transfer may occur at different times to and from the memories, with respect to any given byte of data. The system may incorporate redundant microprocessors, and critical parameters may be checked at periodic intervals in the main program of the accounting microprocessor system.

Abstract: A circuit for tying down a computer bus when the bus is idle by monitoring a series of signals which indicate whether the bus is being used and storing the data signal values on the bus, such that when the bus goes idle the last data value on the bus immediately prior to the bus becoming idle is applied to the bus to hold it at its last known signal value. When a new bus operation is initiated the bus is automatically released for normal operation.

Abstract: A method for automatically completing the entry of the retention and deletion criteria employed by an interactive information handling system to manage the automatic retention and deletion of a relatively large number of electronic documents that are stored in the system by a plurality of end users. The method provides a screen image on a display device in response to the end user advising the system that he wants to assign retention and deletion information to an electronic document. The screen image prompts the end user for a set of required criteria and allows the interactive entry of one or more criteria by the end user directly. The remaining criteria that are not entered directly by the end user are entered automatically based on a logical analysis by said system involving the identity of the criteria that was entered directly and pre-established information stored in said system. The criteria include a document label, an ownership label, a document expiration date and an ownership expiration data.

Abstract: A self time register (STREG) 44 is constructed on a single custom ECL integrated circuit and has provisions for generating its own internal clock signal. The STREG 44 includes a set of latches 80a-80q for temporarily storing the data delivered thereto concurrent with the system clock pulse. Thereafter, the internally generated clock pulse (W.sub.PULS) controls the write operation of the temporary latches into the STREG 44. The STREG has data storage registers including bit storage cells which receive the data in response to the internally generated clock pulse. To selectively output the data, the bit storage cells have emitter-coupled output selectors, and the output selectors for common bits share a common current sink and a common pull-up resistor at which a single-bit output signal is provided from a selected register. Preferably, each bit storage cell has a first output selector for a first data output port, and a second output selector for a second data output port.

Abstract: An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components.

Abstract: A method and apparatus for secure, fast storage and retrieval of information relative to a storage device without interactive checking is characterized by the use of a unique variable range adder. The variable range adder automatically modifies addresses to the storage device and causes data storage and retrieval to conform to the Bell and LaPadula security model, independently of software.

Abstract: A data processor having a split level control store structure, which partitions program memory into a macrocode portion and a microcode portion. The data processor contains two distinct machines, a macromachine and a micromachine. The macromachine includes an instruction sequence controller which detects the macrocode branch instruction before it is perceived by the micromachine, extracts from the branch instruction a macroaddress, and then provides the extracted macroaddress to the program memory as the next sequential instruction address. By "pipelining" the macromachine, the macromachine can "execute" the branch instruction in parallel with, and independent of, the execution by the micromachine of the preceeding instruction.

Abstract: A digital computer system has a central processor unit (CPU). A computer program, entered into the digital computer system for execution thereof, has a program code word embedded at an arbitrary location therein. An addressable programmable array of logic (PAL) is operatively connected to the CPU for receiving a READ signal originated by the CPU at the address of the PAL, the PAL being programmed to output a portion of a preset array code word in a response to the READ signal, and to output the remainder of the array code word in segments in response to subsequent READ signals at the same address. A data bus, connected to receive and transmit the portion and remainders of the array code word to the CPU for comparison with the program code word. The program code word and the array code word are compared and, if identical permit use of the program and do not permit use when the program code word and the array code word are not identical.

Abstract: A sequence of instructions made up of stages is executed sequentially by the processor in a first mode (stack mode) such that, the Nth stage of the Ith instruction is processed simultaneously with the N+1 stage of the I-1 instruction. Similarly the N+1 stage of the I-1 instruction is processed at the sasme time as the N+2 stage of the I-2 instruction and so on. The processing unit maintains the execution of instructions in the same sequence as they were received by the processing unit by executing all sections of an instruction. Even though a stage may not be required for execution of a particular instruction, the processor must wait (i.e., execute a null instruction) for a time equivalent to a stage before processisng the next stage. The invention provides a second mode (non-stack mode) of execution such that unneeded or null instruction stages are bypassed without the processing order of the execution sequence being disturbed.

Abstract: An expansible fixed disk drive data storage subsystem enables attachment of multiple bus-level interface fixed disk drives to a host computer at a single us-level interface fixed disk drive input/output logiical address location.

Abstract: A novel array processor is provided with a plurality of local memories in each data processing element and allows these local memories to be accessed simultaneously, so that a plurality of local memories provided for each data processing element can simultaneously be accessed. The array processor is also has one local memory which is provided with a plurality of output ports for each data processing element, so that all the output ports can simultaneously be accessed, permitting the local memory unit to be accessed simultaneously through a plurality of output ports. The array processor of the present invention decreases the number of memory accesses in each data processing element, with the cumulative effect of achieving a faster speed for the entire data processing system.

Abstract: A method and a system in a virtual machine system controlling a simultaneous run of one or more operating systems (OS's) by use of a virtual machine control program on a real machine including a storage area for each virtual processor constituting the virtual machine for saving a status of each virtual processor, for storing an active flag indicating whether or not the virtual processor is in the active state, and for storing a running priority specified for each virtual processor by the control program wherein when an OS being running issues an instruction to set the processor to the wait state, the instruction is directly executed, a state of the virtual processor being running is stored in the status save area, a processor is selected from processors for which the nonactive state is set, a virtual processor is selected according to the running priority from a group of virtual processors not in the wait state nor in the active state, and a content of the status save area of the virtual processor is set to t

Abstract: The microcomputer has a plurality of register banks, each having a plurality of registers for containing data therein, a bank address register for holding the address of one of the register banks to be accessed and an access control circuit responsive to a bank address signal for putting one of said register banks in accessible condition. Part of the instruction code is utilized to modify the output of the bank address register during a portion of the execution cycle to permit single instruction transfer or arithmetic operations between plural memory banks.

Abstract: A computer file system, in which directory files and real files are organized in a tree structure, includes data items which are recorded in a high-ranking directory file in the tree structure, a high-ranking file management table which records file management data indicative of the assignment relation with low-ranking directory files or real files created below the high-ranking directory file, and a low-ranking file management data which is stored in any of the low-ranking directory files and indicative of the assignment relation between the low-ranking directory file and other low-ranking directory files or real files. The system further includes an assignment relation copy device which copies the file management data of a high-ranking or low-ranking file management table indicative of the assignment relation between the high-ranking or low-ranking directory files or real files into another high-ranking or low-ranking file management table.

Abstract: Data is communicated between redundant channels formatted in blocks having an initial command word followed by a destination code, starting address and a variable number of data words including a word count. The blocks are transmitted between each channel and all of the channels over cross-channel data links, each channel receiving the data blocks and determining the validity thereof by counting the number of data words received and comparing that number to the word count transmitted for that block. An interrupt signal indicative of invalidity of a block is provided in the event of a miscompare. A stop address is generated for each block received for storage at the start address. A memory address is generated for each valid word received for storage in sequence starting immediately after the start address. The next block received has its start address placed immediately at the end of the previously received block.

Abstract: In a multiprocessor system (FIG. 1) wherein each adjunct processor has its own, non-shared, memory (22) the non-shared memory of each adjunct processor (11-12) comprises global memory (42) and local memory (41). All global memory of all adjunct processors is managed by a single process manager (30) of a system-wide host processor (10). Each processor's local memory is managed by its operating system kernel (31). Local memory comprises uncommitted memory (45) not allocated to any process and committed memory (46) allocated to processes. The process manager assigns processes to processors and satisfies their initial memory requirements through global memory allocations. Each kernel satisfies processes' dynamic memory allocation requests from uncommitted memory, and deallocates to uncommitted memory both memory that is dynamically requested to be deallocated and memory of terminating processes.

Abstract: A machine translation system has a display section, an original storage section for storing an original sentence, a dictionary storing linguistical information necessary for translation processing, a translation processing section for translating the original sentence for each predetermined processing unit to obtain a translated sentence, a translation storage section for storing the translated sentence, an edit processing section for executing edit processing for the original and translated sentences, and an input section for inputting instruction information. In addition, the system has a display control section for realizing a first display mode for displaying the original and translated sentences respectively on original and translation display sections of a display screen of the display section, a second display mode for mainly displaying the original sentences on the display screen, and a third display mode for mainly displaying the translated sentences on the display screen.

Abstract: A control and arbitration unit for use in a remote terminal coupled to a system bus over which data encoded in military standard 1553B format is transmitted manages the flow of data between a local processor, a remote terminal interface coupled to the system bus and a local memory so that data transfers occur in an orderly fashion.

Abstract: In a distributed processing system having a least an originating node and a responding node connected through a communication path, the responding node comprising a plurality of processors and a memory device and where each of these processors is capable of accessing information from a corresponding database residing within the memory device, the inventive method involves: storing context information for an associated conversational transaction using a first processor situated within the responding node wherein the context information is stored at a pre-defined address in a first database residing within the memory device and associated with the first processor; producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address; generating within the originating node a second message for transmission fr

Abstract: A latch transfers fetched opcode to PLA for execution at the earliest opportunity following execution of a prior single cycle opcode.