Abstract: A memory writing apparatus for simultaneously writing the same data in a plurality of memories such as PROMs, the apparatus having a master function portion and slave function portions connected to the master function portion. A plurality of memories in which the desired data is to be written by the master function portion are placed in a memory placing section provided in each of the master and slave function portions. The master function portion has a buffer memory which stores the data to be written. Each of the main and slave function portions has a decision circuit for comparing the data actually written in each of the memories with the data stored in the buffer memory.

Abstract: A data processing security device, attached to computing equipment, inserts labels into a data stream that indicate security controls for the data. The security device may also be configured to detect security labels within a data stream and inhibit the flow of data. It also may replace data within a data stream if it detects labeled fields which indicate that privacy should be imposed.

Abstract: A computer system includes a processing unit and an external storage holding a virtual data set including an address translation table in addition to data and program. The processing unit includes a real storage for holding an address translation table transferred from the external storage when the virtual data set is opened and an address translation mechanism for making access to the real storage by translating the virtual address to the real address with the aid of the address translation table. When the data required by the processing unit is absent on the real storage, the processing unit transfers the virtual address to the external storage and holds the data transferred from the external storage on the real storage.

Abstract: A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with application programs written for slower speed microprocessors. A logic means is included responsive to a speed select signal which does not change the speed of the microprocessor oscillator (clock) but rather changes the length of a wait state or "STOP" state of the microprocessor. In the STOP state the microprocessor (CPU) does not run bus cycles until the timer times out thereby releasing the CPU STOP. By varying the length of the time delay of the one-shot timer, the microprocessor simulates microprocessor speed changes which have the appearance of earlier generation computers with older microprocessors.

Abstract: Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for non-cacheable devices are not in that predetermined range. Since by definition cacheable devices are 32-bit devices, pipelined operation is allowed only if the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are non-cacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining.

Abstract: The system providing a guidance for the command entry to an interactive computer recognizes the hierarchical rank of productions and displays command explanatory messages below the rank of production to which the command in need of explanation belongs. Displaying commands of one or two ranks relieves the operator from the annoyance of useless display reading.

Abstract: A data processor which is so constructed that an operation code decoder decodes an operation code in an instruction to be processed comprising an operation code and an operand descriptor, and an addressing mode decoder decodes the operand descriptor, so that when the addressing mode of the operand is detected to be a specified addressing mode, for example, a register direct addressing mode, an entry address of microinstruction generated by the operation code decoder is modified, thereby enabling the entry address, different in microinstruction during the specified addressing mode and others, to be generated without increasing the number of product terms of a PLA in an instruction decoder.

Abstract: A technique for performing joins in parallel on a multiple processor database system effectively deals with data skew. The join operation is performed in three stages with an optional fourth stage. The first stage is a preparatory stage, the detail of which depends on the underlying join algorithm used. This preparatory stage provides pre-processing the results of which are used in the following stage as the basis for defining subtasks for the final join operation. The data provided in the first stage is used in the second stage to both define subtasks and to optimally allocate these subtasks to different processors in such a manner that the processors are close to equally loaded in the final join operation, even in the presence of data skew. This second stage is an assignment stage the details of which depend on the underlying join algorithm.

Abstract: A method and apparatus for performing storage and retrieval in an information storage system is disclosed which uses the hashing technique. In order to prevent contamination of the storage medium by automatically expiring records, a garbage collection technique is used which removes all expired records in the neighborhood of a probe into the data storge system. More particularly, each probe for insertion, retrieval or deletion of a record is an occasion to search the entire chain of records found for expired records and then removing them and closing the chain. This garbage collection automatically removes expired record contamination in the vicinity of the probe, thereby automatically decontaminating the storage space. Because no long term contamination can build up in the present system, it is useful for large data bases which are heavily used and which require the fast access provided by hashing.

Abstract: An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: A circuit is provided for control and data transfer between a standard data storage device interface and one of a choice of several host computers. Parallel transition memories in conjunction with a buffer memory under common control of a buffer manager increase the transfer efficiency between the data storage unit and the host computer. Selectable register banks provide interface compatibility with multiple host computers for implementation of the invention.

Abstract: The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N<n, in register (16). The frame characters to be sent on lines (6) are stored into register (28), and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive logical "1's" as a function of the value of the N bit and as a function of the bits of the previous character, to store into register (32), the bits which are sent on lines (6).

Abstract: A computer system having plural nodes interconnected by a common broadcast bus. Each node has memory and at least one node has a processor. The system has a dynamically configurable memory which may be located within the system address space of a distributed system architecture including memory within each node having a processor and the memory resident within other nodes. The memory in the system address space is addressable by system physical addresses which are isolated from the physical addresses for memory in each node. The node physical addresses are translatable to and from the system physical addresses by partition maps located in partition tables at each node. Memory located anywhere in the distributed system architecture may be partitioned dynamically and accessed on a local basis by programming the partition tables, stored in partitioning RAMs.

Abstract: A method for allowing a system administrator, application programmer, and/or program user to adjust the processor assignment function in a multiprocessor system. The system administrator controls the assignment function by defining certain system variables and flags. The application programmer can adjust the assignment function by causing allocation parameters to be passed in a system call before execution of the assignment function. To adjust the assignment function, the program user executes a system command that inserts similar allocation parameters into the program object code file stored in a file system on the multiprocessor system. The program executing the assignment function is responsive to the system variables and flags as well as the allocation parameters and performs the assignment function as it has been adjusted on a system, program or user level basis.

Abstract: A system for linking elements representing stored information in a data base comprising a link structure formed in a section of the data base independent of the elements, a pointer in the link structure indicating the location of a first element, and a second pointer in the link structure indicating the location of a second element. The data base contains items comprising textual data and a plurality of categories into which the items may be categorized such that each item may be linked to more than one category. The invention automatically assigns an element in a data base to a parent category if it has been assigned to a child category of the parent. The invention will allow a user to modify data in a data base in a view mode, and will resolve ambiguities by guessing as to the most likely interpretation intended by the user. The invention will allow a user to change the number or organization of categories in the data base while the user is in a view mode.

Abstract: A basic input and output system program, (BIOS) includes a 16-bit interface hard disk controller, (HDC) control routine and an 8-bit interface HDC control routine, and also includes an automatic HDC type determination routine. The 16-bit interface HDC has an inherent I/O address (I/O port), but the 8-bit interface HDC has no inherent I/O address (I/O port). By utilizing this fact, a CPU writes specified data at the I/O address inherent to the 16-bit interface HDC. The CPU then reads out the data from the I/O address, and compares the read data with the written data. If a coincidence is obtained, the CPU determines that the 16-bit interface HDC is used, and sets up a 16-bit interface HDC control routine. On the other hand, if no coincidence is obtained, the CPU determines that the 8-bit interface HDC is used, and sets up an 8-bit interface HDC control routine.

Abstract: In pyramidal data storage, a single address is used to identify any arbitrary large group of related data. The data items are stored in the form of multi level progressions in which lower level data items are combined to form higher and higher level data items in the form of a pyramid. The invention provides a method and apparatus to store and retrieve pyramidal data groups from a computer memory.

Abstract: A circuit for delaying at least one high bit rate data train, the circuit comprising: first (25) and second (26) first-in-first-out (FIFO) type registers having "m" inputs and "n" words in series; a binary counter (27) delivering a most significant bit signal (MSB); a write/read control circuit (28) for controlling writing and reading in said register (25, 26) and comprising: a circuit for switching a clock signal (H) alternatively to each of the two registers (25, 26) in order to write in one of the two registers while simultaneously reading from the other, and vice versa; a circuit (33, 34) for dynamically resetting said registers (25, 26) to zero immediately prior to each write stage; and a circuit (35) for generating an output enable signal for controlling said registers to enable the previously input data to be output therefrom after a delay of "n" clock periods since the beginning of a write stage.

Abstract: A memory management unit in which logical addresses are translated into physical addresses is provided that comprises a segment register section that is composed of a plurality of segment registers; a segment address decoder for selecting a desired segment register in the segment register section; and an effective-address selection register from which an effective address for the desired segment register is fed to the segment address decoder. A part of the logical address is used as the effective address and the remaining part of the logical address is used as an expanded part of the physical address.

Abstract: In an interrupt control circuit for use with one of a plurality of modules connected to a multi master bus (12) which accepts an interrupt request from another module through a multi-master bus (20), an interrupt vector number is generated corresponding to an interrupt source, and is sent to a CPU (22) within the module. In addition to a conventional first vector number generating circuit (18) the control circuit includes a second vector number generating circuit (16) which transforms a vector number (N.sub.2) corresponding to a kind of interrupt when the first vector number (N.sub.