Patents Examined by Gene Auduong
  • Patent number: 10332593
    Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takahiko Sasaki, Go Shikata, Tomonori Kurosawa, Rieko Funatsuki
  • Patent number: 10236884
    Abstract: A semiconductor device with lower power consumption and an electronic device including the same are provided. To reduce leakage current flowing in a word line driver circuit, a switching element is provided, specifically, between the word line driver circuit and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the word line driver circuit. Furthermore, to reduce the stand-by power due to precharge of a bit line, a switching element is provided in a bit line driver circuit, specifically, between the bit line and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the bit line driver circuit.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Wataru Uesugi
  • Patent number: 10236043
    Abstract: Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 19, 2019
    Assignee: Altera Corporation
    Inventor: Pohrong Rita Chu
  • Patent number: 10224106
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: March 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Maejima
  • Patent number: 10210892
    Abstract: A magnetic recording medium includes a support, a recording layer, and a protective layer provided on at least one surface of the support and containing plate-shaped particle powder. The plate-shaped particle powder is stacked in an overlapping manner in a thickness direction of the protective layer such that main surfaces of plate-shaped particles face a surface of the support, and the plate-shaped particles have an average plate ratio of 60 or more.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: February 19, 2019
    Assignee: Sony Corporation
    Inventors: Eiji Nakashio, Minoru Yamaga, Jun Takahashi
  • Patent number: 10210947
    Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Shunya Nagata, Shinji Tanaka
  • Patent number: 10204680
    Abstract: According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Patent number: 10203380
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignees: SK Hynix Inc., Toshiba Memory Corporation
    Inventors: Ku-Youl Jung, Guk-Cheon Kim, Toshihiko Nagase, Daisuke Watanabe, Won-Joon Choi, Youngmin Eeh, Kazuya Sawada
  • Patent number: 10204003
    Abstract: A failure region is specified when a failure occurs in a non-volatile semiconductor memory. When a device controller reads data stored in a specific page in a plurality of non-volatile semiconductor memories to detect an uncorrectable error (UE) of the data stored in the specific page, the device controller executes a diagnosis process including specifying a specific storage circuit that is a storage circuit including the specific page, reading data stored in a part of blocks of the specific storage circuit, and specifying, on the basis of a result of reading data stored in the block, a failure region in the specific storage circuit.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: February 12, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kenta Ninose, Takuji Itou, Fumio Yoshioka, Takashi Tsunehiro, Go Uehara, Shigeo Homma
  • Patent number: 10199097
    Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jason Brand, Jason Snodgress
  • Patent number: 10192615
    Abstract: An One-Time Programmable (OTP) memory is built in at least one of semiconductor fin structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one fin. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one fin can be built on a common well or on an isolated structure that has at least one MOS gate dividing fins into at least one first active region and a second active region.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 29, 2019
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10191458
    Abstract: A configurable, connectorized system for providing RTU monitoring of field digital and analog parameters and transmitting data to the Central PLC system dramatically reduces the number of wire connections that must be made to connect sensors and actuators to a PLC system. The system is also extremely rugged and safe to be located in a hazardous environment.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 29, 2019
    Assignee: 3-CI Partnership
    Inventors: Steven Paul Cunningham, Logan S. Gunthorpe
  • Patent number: 10192632
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells coupled between a common source line and a bit line, and a voltage generator applying operating voltages to word lines coupled to the memory cells or discharging potential levels of the word lines, wherein during a program verify operation, the voltage generator applies a program verify voltage and a pass voltage as the operating voltages to the word lines, and subsequently applies a set voltage to the common source line during a period in which the memory cells are turned on.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 29, 2019
    Assignee: SK Hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10186321
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
  • Patent number: 10176885
    Abstract: A semiconductor memory apparatus includes a comparison circuit generating a detection code in response to stored data and expected data, a counting circuit generating a counting code in response to the detection code, a selection code output circuit outputting one of a plurality of expected codes as a selection code in response to a selection signal, and a plurality of signal storage circuits. A comparison result output circuit including a plurality of signal storage circuits which stores a comparison result of a comparison between the counting code and the selection code in one signal storage circuit among the plurality of signal storage circuits according to the selection signal, and a value stored in one signal storage circuit among the plurality of signal storage circuits is output as a result signal in response to an output enable signal.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang
  • Patent number: 10176856
    Abstract: A semiconductor memory apparatus may be provided. The semiconductor memory apparatus may include a row decoder configured to generate one or more row decoding signals based on a plurality of row addresses. The semiconductor memory apparatus may include a column decoder configured to generate one or more column decoding signals based on a plurality of column addresses.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventor: Kee Teok Park
  • Patent number: 10176877
    Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: January 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasushi Nagadomi
  • Patent number: 10170166
    Abstract: The data transmission apparatus includes a prior stage shift register circuit and a plurality of rear stage shift register circuits. The prior stage shift register circuit is coupled to a sense amplifying device of the memory, receives sensed data from the sense amplifying device and outputs a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal. The plurality of rear stage shift register circuits are coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads. The plurality of rear stage shift register circuits respectively receive the readout data and respectively bitwise transport the readout data to the pads according to a clock signal. Wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 1, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Oron Michael, Poongyeub Lee
  • Patent number: 10170171
    Abstract: Techniques are described that enable a high-capacity memory chip based on three-dimensional SpinRAM cells and modules, and support electronics, at least some of which, are implemented with all-metal solid-state components.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: January 1, 2019
    Assignee: Integrated Magnetoelectronics Corporation
    Inventors: Edward Wuori, Richard Spitzer
  • Patent number: 10163476
    Abstract: A method of operating a tracking circuit of a memory device includes charging a node of the tracking circuit to a first predetermined voltage level, the first node being electrically coupled with a first load device. A first plurality of tracking cell transistors are activated to discharge the first node toward a second predetermined voltage level. A reset signal is generated based on a signal at the first node. The reset signal may correspond to a waiting period for reading a memory cell of the memory device.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY, LTD.
    Inventors: Kuoyuan (Peter) Hsu, Jacklyn Chang