Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

Abstract: A dual interlocked storage cell (DICE) latch may be provided. A semiconductor device may be provided. The semiconductor device may include a DICE latch.

Abstract: The present disclosure relates to semiconductor devices and discloses a method for operating a flash memory. When a read operation is performed on a flash memory unit, a potential of a first control line connected to gates of select gate PMOS transistors located in a same row is switched from a positive supply voltage to 0V. Since it is not required to switch the potential from a positive voltage to a negative voltage, the power consumption of the pump circuit is significantly reduced. In addition, a read current of the flash memory unit selected for reading can accurately represent the status of the unit being read thanks to the appropriate settings of the gate oxide layer thickness and the threshold voltage of the select gate PMOS transistor. Furthermore, high-voltage devices are removed from the read path and only low-voltage devices are used, so that the reading speed can be significantly improved during the read operation.

Abstract: A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address storage circuit may store a first repair address and a second repair address. The address comparison circuit may generate a first comparison signal by comparing an input address and the first repair address, and may generate a second comparison signal by comparing the input address and the second repair address. The word line selection circuit may generate a first redundancy word line select signal corresponding to the first comparison signal and a second redundancy word line select signal corresponding to the second comparison signal, based on the first comparison signal and the second comparison signal.

Abstract: A semiconductor device includes a control signal generation circuit and an input/output (I/O) control circuit. The control signal generation circuit generates first and second read control signals and first and second write control signals. One of the first and second read control signals and one of the first and second write control signals is selectively enabled according to a combination of first and second addresses for selecting a first I/O line or a second I/O line. The I/O control circuit outputs read data loaded on first and second internal I/O lines through any one of the first and second I/O lines in response to the first and second read control signals. In addition, the I/O control circuit outputs input data through any one of the first and second I/O lines in response to the first and second write control signals.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, and a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks. The semiconductor memory device may include control logic configured to control the peripheral circuit so that a pre-program voltage pulse is applied both to the dummy word lines and to the normal word lines, and dummy word line voltages to be applied to the dummy word lines may be respectively controlled while an erase voltage is applied to a common source line of the selected memory block.

Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.

Abstract: A magnetoresistive memory device that stores data in the reference portion of spin-torque memory cells provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, along with techniques for recovering data stored in the reference portions of memory cells.

Abstract: To perform refresh without saving data, and prevent corruption of data in non-volatile memories. A number-of-write-operations information holding unit holds number-of-write-operations information, which is the number of write operations of a non-volatile memory to which access is made in units of pages which are divided by a page size. A determination unit determines whether or not refresh, which is reversing of values of all memory cells constituting the pages, is necessary on the basis of the held number-of-write-operations information. A write control unit further performs the refresh in addition to writing when the refresh is necessary on the basis of a result of the determination at a time of the writing with respect to the pages.

Abstract: A ferroelectric random access memory (FeRAM) array includes (a) a first section of FeRAM cells sharing a first plate line and a word line; and (b) a second section of FeRAM cells sharing a second plate line and the word line, wherein the first plate line and the second plate line are electrically unconnected, and wherein only the first section of FeRAM cells or the second section of FeRAM cells, but not both, are selected for a read operation at any given time. In each section of the FeRAM cells, a plate line selection cell connects the corresponding plate line to a plate line selection line. Each FeRAM cell in each section is read or written over a pair of bit lines running in a direction transverse to the word line of the section, and the plate line selection line runs along a direction parallel to the bit lines.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: A method for programming a non-volatile memory device includes programming a lower bit in a memory cell included in the non-volatile memory device, reading the lower bit programmed in the memory cell before programming an upper bit in the memory cell, determining a threshold voltage of the memory cell according to a result of reading the lower bit, determining a type of the memory cell using the threshold voltage, and supplying one of a plurality of pulses to a bit line connected to the memory cell according to the determined type of the memory cell.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Abstract: A memory device includes a first memory array comprising a first bit cell configured to store a first logical state; and a reference signal provision (RSP) unit, coupled to the first memory array, and configured to provide a first reference signal that represents an average of a discharging rate and a leakage rate of a second memory array. In an embodiment, the first logical state stored by the first bit cell is read out using the first reference signal.

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: A memory circuit includes a plurality of memory cells and a tracking circuit. Each memory cell of the plurality of memory cells includes a cell transistor corresponding to a predetermined transistor configuration. The tracking circuit includes a first tracking bit line, a first tracking word line, a reference voltage node, and a first plurality of tracking cells. Each tracking cell of the first plurality of tracking cells includes a cell transistor corresponding to the predetermined transistor configuration. The cell transistors of the first plurality of tracking cells are electrically coupled in series between the first tracking bit line and the reference voltage node, and gate terminals of the cell transistors of the first plurality of tracking cells are electrically coupled with the first tracking word line.