Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: An input circuit of a memory device includes an input receiver to receive an input signal, a clock receiver to receive a clock signal, a data latch, an input signal delay path coupled to the input receiver and configured to provide a delayed internal input signal to the data latch, a first clock signal delay path coupled to the clock receiver and configured to provide a first delayed internal clock signal, a second clock signal delay path coupled to the input receiver and configured to provide a second delayed internal clock signal, and a multiplexer coupled to receive and select one of the first delayed internal clock signal and the second delayed internal clock signal in response to a test mode control signal, and to provide the selected signal to the data latch.

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

Abstract: Artificial ices enable the study of geometrical frustration by design and through direct observation. It has, however, proven difficult to achieve tailored long-range ordering of their diverse configurations, limiting both fundamental and applied research directions. An artificial spin structure design is described that produces a magnetic charge ice with tunable long-range ordering of eight different configurations. A technique is also developed to precisely manipulate the local magnetic charge states and demonstrate write-read-erase multi-functionality at room temperature. This globally reconfigurable and locally writable magnetic charge ice provides a setting for designing magnetic monopole defects, tailoring magnetics and controlling the properties of other two-dimensional materials.

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract: Hybrid circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a power saving mode. At normal operation mode, a hybrid circuit operates in the same ways as typical CMOS circuits. At power saving mode, the standby leakage current of the circuit is reduced significantly. Typically, most parts of a hybrid circuit stay in power saving mode. A circuit block is switched into normal operation mode when it needs to operate at full speed. The resulting circuits are capable of supporting ultra-low power operations without sacrificing performance. Hybrid circuits can be implemented on integrated circuits comprising multiple-gate MOS transistors.

Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

Abstract: A disclosed example includes generating a first binary value corresponding to a first sensed threshold voltage of a multi-level cell (MLC) memory cell corresponding to a first time at which a bias voltage is applied to a temporary bias cache capacitor of the MLC memory cell; generating a second binary value corresponding to a second sensed threshold voltage of the MLC memory cell corresponding to a second time at which the bias voltage is not applied to the temporary bias cache capacitor of the MLC memory cell; and based on the first and second binary values, selecting whether to program the MLC memory cell using a full program pulse or a partial program pulse.

Abstract: Reduced errors when sensing non-volatile memory are provided by applying a current spike or preconditioning current for a group of memory cells included a selected cell. During a sense operation, a preconditioning current can be passed through a group of non-volatile memory cells. The preconditioning current is provided prior to applying at least one reference voltage to a selected word line. The preconditioning current may simulate a cell current passing through the channel during a verification phase of programming. The preconditioning current can modify a channel resistance to approximate a state during verification to provide a more stable threshold voltage for the memory cells. Preconditioning currents may be applied selectively for select reference levels, select pages, and/or select operations. Selective application of preconditioning currents based on temperature is also provided.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Abstract: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.

Abstract: A Field Sub-bitline NOR-type (FSNOR) flash array and its operating methods are disclosed. In contrast to the conventional NOR flash array, the FSNOR array is configured in column with multiple 90° rotated NOR pairs linked by field side sub-bitlines to achieve the minimum 4F2 cell size. The FSNOR flash array is divided into multiple sectors by selection transistors for connecting the even/odd sub-bitlines to the global main first metal bitlines. For each FSNOR sector, the two drain electrodes of column-adjacent NOR pairs form the even/odd sub-bitlines separated by trench field oxides respectively, and the common source electrodes of NOR pairs in a column form the common diffusion source lines tied with metal contacts connected to the first metal common source lines. The FSNOR flash array design has enhanced the electrical isolation of the selected NVM cell devices from the unselected NVM cell devices.

Abstract: The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply. The word line level fixing circuit includes multiple level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply.

Abstract: Embodiments of an electroentropic memory device comprising an array of electroentropic storage devices (EESDs) are disclosed, as well as methods of making and using the electroentropic memory device. The memory device includes a plurality of address lines arranged in rows to select a row of the EESDs and a plurality of data lines arranged in columns to select a column of the EESDs, wherein each EESD is coupled in series between an address line connected to one side of the EESD and a data line connected to an opposing side of the EESD. The memory device may have a stacked architecture with multiple layers of address lines, data lines, and EESDs. The disclosed electroentropic memory devices are operable in ROM and RAM modes. EESDs in the disclosed electroentropic memory devices may include from 2-4096 logic states and/or have a density from 0.001 kb/cm3 to 1024 TB/cm3.

Abstract: A memory device includes a first memory array comprising a first bit cell and a second bit cell that are configured to provide a first reference signal and a second reference signal, respectively; a second memory array comprising a third bit cell that is configured to store a first logical state; a reference signal provision (RSP) unit, coupled to the first memory array, and configured to short the first and second reference signals so as to provide an averaged reference signal; and a sensing amplifier, coupled between the RSP unit and the second memory array, and configured to use the averaged reference signal to read out the first logical state stored by the third bit cell.

Abstract: A memory device may include a first inverter, a second inverter, and a control transistor. The control transistor is electrically connected to each of an output terminal of the first inverter and an input terminal of the second inverter for controlling an electrical connection between the output terminal of the first inverter and the input terminal of the second inverter.

Abstract: Disclosed is a memory test method including receiving a memory test command, receiving pattern information for generating a data pattern to be written in a memory cell, and programming the memory cell according to the pattern information. According to this method, it is not required to receive external data to be programmed in a cell array.

Abstract: A programmable integrated circuit, includes an external port, a configuration memory, a hardened write path between the external port and the configuration memory and a soft read path between the configuration memory and the external port, wherein configuration data stored in the configuration memory is only read through the soft read path.