Patents Examined by Gene M. Munson
  • Patent number: 7262467
    Abstract: An over-voltage protection device includes a substrate including an upper surface and a lower surface; a first electrode provided on the upper surface of the substrate; a second electrode provided on the lower surface on the substrate; a first conductive layer overlying the lower surface of the substrate, the first conductive region being a conductive region of a first type; a plurality of first conductive regions provided proximate the upper surface of the substrate, the plurality of first conductive regions being conductive regions of the first type; and a plurality of second conductive region provided proximate the upper surface of the substrate, the plurality of second conductive region being conductive regions of a second type. The plurality of the first conductive regions are provided in an alternating manner with the plurality of second conductive regions. The first electrode is contacting the plurality of the first and second conductive regions.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: August 28, 2007
    Assignee: IXYS Corporation
    Inventor: Ulrich Kelberlau
  • Patent number: 7233051
    Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: June 19, 2007
    Assignee: Intel Corporation
    Inventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia
  • Patent number: 7214999
    Abstract: An exemplary system and method for providing an integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS host wafer (460) bonded with a monocrystalline, optically active donor wafer (300); a photosensing element (390) integrated in said optically active donor wafer (300) having an interconnect via (505, 495, 485) substantially decoupled from the photosensing element (390), wherein the host (460) and donor (300) wafers are bonded through the optically active material in a region disposed near a metalization surface (450, 455, 445) of the CMOS layer (460) in order to allow fabrication of the interconnect (505, 495, 485). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: May 8, 2007
    Assignee: Motorola, Inc.
    Inventors: Paige Holm, Jon J. Candelaria
  • Patent number: 7205576
    Abstract: A light emitting device and a method of manufacturing the same are provided. A light emitting device has a structure wherein a substrate, an n-type clad layer, a light emitting layer, a p-type clad layer, an ohmic contact layer, and a reflective layer are successively stacked. The ohmic contact layer is formed by adding an additional element to an indium oxide. According to the light emitting device and the method of manufacturing the same, the characteristics of ohmic contact with a p-type clad layer is improved, thus increasing the efficiency and yield of wire bonding during packaging FCLEDS. Also, it is possible to increase the light emitting efficiency and life span of light emitting devices due to the low contactless resistance and the excellent electric current and voltage characteristic.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: April 17, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: June-o Song, Dong-seok Leem, Tae-yeon Seong
  • Patent number: 7180149
    Abstract: A semiconductor package of the invention comprises: a semiconductor element provided with a circuit element on one surface of a semiconductor substrate; an external wiring region provided on an other surface of the semiconductor substrate; a support substrate disposed on the one surface of the semiconductor substrate; an electrode pad disposed on the one surface of the semiconductor substrate; and a through-electrode which extends from the electrode pad through to the other surface of the semiconductor substrate.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: February 20, 2007
    Assignees: Fujikura Ltd., Olympus Corporation
    Inventors: Satoshi Yamamoto, Tatsuo Suemasu, Sayaka Hirafune, Toshihiko Isokawa, Koichi Shiotani, Kazuya Matsumoto
  • Patent number: 7180185
    Abstract: A semiconductor device includes a passivity film, an insulating film and an encapsulating layer, all of which are formed, in this order, on the surface of a semiconductor substrate provided with a connecting pad, and a bump electrode electrically connected to the connecting pad via a wiring passing through a first opening defined in the passivation film and a second opening defined in the insulating film. The bump electrode has a leading end portion exposed from the surface of the encapsulating layer.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: February 20, 2007
    Assignee: Oki Electric Industry Co., Ltd
    Inventor: Takashi Ohsumi
  • Patent number: 7180924
    Abstract: The invention provides a semiconductor unit and a semiconductor apparatus having a low electric resistance as a whole, even when the electric resistance of a functional layer or a semiconductor substrate is high. A method of making the semiconductor unit and apparatus is also provided. An electrooptic apparatus and an electronic apparatus are also provided. A semiconductor apparatus includes a predetermined substrate and a semiconductor unit bonded to the substrate. The semiconductor unit includes a highly conductive layer and a functional layer including a semiconductor element.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: February 20, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Takayuki Kondo
  • Patent number: 7176495
    Abstract: Disposing the light absorption layer formed in contact with a polycrystal silicon layer of a bottom gate type polycrystal silicon TFT allows a depletion layer formed between drain and channel forming regions to extend further into the inside of the light absorption layer, resulting in collection of photo carriers produced in the depletion layer into the channel forming region. The photo carriers collected into the channel forming region are subsequently collected into the source region to be output as large photocurrents by high mobility of the polycrystal silicon.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: February 13, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Masayuki Sakakura
  • Patent number: 7176500
    Abstract: The present invention achieves improvement of the color reproducibility, color rendering properties and light emitting efficiency of a white light emitting diode. The present invention is a red fluorescent material composed of a europium doped lithium lanthanum niobate represented by a general formula of LiLa1-xEuxNb2O7 (0<x?1). The red fluorescent material can efficiently converts light in the light emission wavelength range from 350 to 410 nm of an ultraviolet light emitting diode into red light, and can efficiently converts blue light at 465 nm and green light at 538 nm into red light.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: February 13, 2007
    Assignee: NEC Corporation
    Inventors: Ryo Yoshimatsu, Hisashi Yoshida
  • Patent number: 7166879
    Abstract: A photogate-based photosensor for use in a CMOS imager exhibiting improved short wavelength light response. The photogate is formed of a thin conductive layer about 50 to 3000 Angstroms thick. The conductive layer may be a silicon layer, a layer of indium and/or tin oxide, or may be a stack having an indium and/or tin oxide layer over a silicon layer. The thin conductive layer of the photogate permits a greater amount of short wavelength light to pass through the photogate to reach the photosite in the substrate, and thereby increases the quantum efficiency of the photosensor for short wavelengths of light.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 7164153
    Abstract: A thin film transistor array panel is provided, which includes: a substrate including a plurality of pixel areas; a semiconductor layer formed on the substrate and including a plurality of pairs of first and second semiconductor portions in respective pixel areas; a first insulating layer formed on the semiconductor layer; a gate wire formed on the first insulating layer; a second insulating layer formed on the gate wire; a data wire formed on the second insulating layer; a third insulating layer formed on the data wire; a pixel electrode formed on the third insulating layer and connected to the data wire, wherein width and length of at least one of the first and the second semiconductor portions vary between at least two pixel areas.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: January 16, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-Gyeong Lee, Sook-Young Kang, Myung-Koo Kang, Hyun-Jae Kim, James S. Im
  • Patent number: 7151295
    Abstract: In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: December 19, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshitake Yaegashi, Koki Ueno
  • Patent number: 7148508
    Abstract: The invention achieves stable performance, such as low parasitic capacitance generated at conductive components. Components having a low dielectric constant of 4 or less are disposed on a base member. Functional films partitioned by the low-dielectric-constant components are also provided.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: December 12, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Takashi Miyazawa
  • Patent number: 7145203
    Abstract: A high-voltage graded junction LDMOSFET includes a substrate of a first conductivity type, a well of the first conductivity type disposed in the substrate, a first region of a second conductivity type disposed in the well of the first conductivity type, a source terminal coupled to the first region of the second conductivity type, a well of the second conductivity type disposed in the substrate, a second region of the second conductivity type disposed in the well of the second conductivity type, a drain terminal coupled to the second region of the second conductivity type, a region of the first conductivity type disposed in the substrate, a body terminal coupled to the region of the first conductivity type, a graded-junction region formed of material of the first conductivity type separating the well of the first conductivity type and the well of the second conductivity type, the material of the first conductivity type in the graded-junction region doped at least an order of magnitude less than the wells, a d
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: December 5, 2006
    Assignee: IMPINJ, Inc.
    Inventor: Bin Wang
  • Patent number: 7145253
    Abstract: Disclosed is a semiconductor device and its manufacturing method. By way of example, the semiconductor device includes a semiconductor die for sensing an external physical quantity, an insulating gel covering the semiconductor die, and an encapsulant which covers the insulating gel while the insulating gel is partially exposed to the exterior. Also, another semiconductor device further includes a dummy plate which has a hole and is seated on the insulating gel. In the manufacturing method of a semiconductor device, a mold having a through hole is provided and the through hole include a structure consisting of a movable pin and a spring for absorbing the expansion of the insulating gel during an encapsulation process. Also, another manufacturing method of a semiconductor device includes performing the encapsulation while the dummy plate is seated on the insulating gel.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: December 5, 2006
    Assignee: Amkor Technology, Inc.
    Inventors: Tae Soo Kim, Young Hyo Eun, Jicheng Yang, Jong Wook Park, David DoSung Chun, Hee Yeoul Yoo
  • Patent number: 7138676
    Abstract: A semiconductor device in which a plurality of rows are set along an X direction and a plurality of columns are set along a Y direction orthogonal to the X direction, comprises a first element region including a first trench disposed in a first column at one end thereof and a second trench disposed in a second column parallel to the first column at the other end thereof; a second element region including a third trench disposed at a position closer to the second trench than the first trench in the first column at one end thereof and a fourth trench disposed in the second column at the other end thereof; and a third element region including a fifth trench disposed at a position closer to the fourth trench than the third trench in the first column at one end thereof and a sixth trench disposed in the second column at the other end thereof.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: November 21, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshinori Matsubara
  • Patent number: 7135710
    Abstract: A first cladding layer of a first conductivity type formed above a crystal substrate, an active layer formed above the first cladding layer, a diffusion prevention layer formed on the active layer and preventing an impurity from diffusing into the active layer, an overflow prevention layer of a second conductivity type, the second conductivity type being different from the first conductivity type, which is formed on the diffusion prevention layer and prevents an overflow of carriers implanted into the active layer, and a second cladding layer of the second conductivity type formed above the overflow prevention layer are provided.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: November 14, 2006
    Assignee: Kyowa Patent and Law Office
    Inventors: Akira Tanaka, Masaaki Onomura
  • Patent number: 7132722
    Abstract: A physical quantity sensor is constituted using a plurality of piezoelectric sensors each having first and second semiconductor layers realizing resistances and terminals, and a conductive weight portion in relation to an opening of an insulating film that partially exposes the main surface of a substrate. Both the semiconductor layers are elongated from the periphery of the opening on the insulating film inwardly into the opening so as to three-dimensionally support the conductive weight portion in a floating manner, thus realizing three-dimensional displacement. A capacitance electrode layer is arranged in the bottom of the opening on the main surface of the substrate so as to establish capacitance with the conductive weight portion. The displacement of the conductive weight portion is detected based on resistance variations and capacitance variations. Thus, it is possible to detect physical quantity such as acceleration, vibration, and inclination with a reduced chip size.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: November 7, 2006
    Assignee: Yamaha Corporation
    Inventor: Toshio Ohashi
  • Patent number: 7129536
    Abstract: A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: October 31, 2006
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bomy Chen, Sohrab Kianian, Yaw Wen Hu
  • Patent number: 7122864
    Abstract: A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: October 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima