Abstract: A thin film transistor array substrate and a method for manufacturing the same is disclosed, in which it is possible to prevent mobile ions contained in a substrate from penetrating into a semiconductor layer by the gettering effect or neutralization in case soda lime glass is used for the substrate. The method includes forming a buffer layer on a substrate; doping impurity ions in the buffer layer; and forming a pixel electrode and a thin film transistor including a semiconductor layer on the buffer layer.

Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.

Abstract: A semiconductor apparatus includes a substrate with a peripheral edge. A plurality of devices are situated on the substrate and adjacent the peripheral edge, with each device including a first end adjacent the peripheral edge and a second end opposite the first end. A connector port is located between the first end and the second end on each device. A bonding pad is situated atop a portion of each device and coupled to each device by a connector connected to the connector port. Each connector has a connection path of approximately equal length.

Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.

Abstract: Resistance or side electrodes of a chip resistor is prevented from being lost due to chemical reaction with NaCl contained in human sweat and so on when human sweat, seawater, etc. are adhered thereto. The chip resistor comprises an insulating substrate, thick-film upper surface electrodes formed at opposite ends of the top surface of the insulating substrate, a thin-film resistance made of a constituent material not reacting with NaCl, and formed so as to be extended over the upper surface of the insulating substrate and respective portions of the upper surface of the thick-film upper surface electrodes, thick-film back surface electrodes formed at spots on the back surface of the insulating substrate, corresponding to the thick-film upper surface electrodes, respectively, and thick-film side surface electrodes connecting the thick-film back surface electrodes with respective portions of the thick-film upper surface electrodes, exposed out of the thin-film resistance, respectively.

Abstract: A compound filled in lead packaging integrated circuit product includes a substrate made of a metallic material, a metallic protection layer formed on a top face of the substrate for protection of the substrate and surface mounting of an electrical appliance, the electrical appliance securely mounted on the protection layer and a compound or encapsulation material surrounding the substrate and the electrical appliance for supporting the substrate.

Abstract: The present invention provides a hetero-bipolar transistor having a new configuration of the interconnection. The bipolar transistor of the present invention includes the collector mesa, having the base and collector layers therein, includes a first side having a normal mesa surface and extending along the [01-1] orientation, and a second side having a reverse mesa surface and extending along the [011] orientation. The present HBT has a base interconnection, a portion of which diagonally intersects the first side of the collector mesa, accordingly, the breaking of the interconnection may not occur and the high frequency performance of the HBT may be enhanced because the width of the collector mesa is not necessary to widen to disposed the base interconnection on the first side.

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Abstract: An opto-electronic device configured as a photodetector has a capacitor and/or resistor monolithically formed on a surface of the photodetector. The capacitor capacitively couples the AC ground of the photodetector to the bias terminal of the photodetector. The on chip capacitor design eliminates the inductance of external circuit traces between the power supply and an external capacitor. The resistor forces the AC return current of the photodetector through the AC ground in preference to the typical (DC bias terminal) path. Combinations of capacitors and resistors are particularly effective in reducing crosstalk among adjacent detectors in arrays.

Abstract: A solid-state imaging device that can include a pixel array where a plurality of unit pixels including a photo diode and an insulated gate field effect transistor for detecting photocharges are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can include a drain control circuit that provides any of constant voltage, a constant current, and constant charges to a drain diffused region. The control circuit previously forward biases a junction region between a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type by any of the constant voltage, the constant current, and the constant charges, that is provided from the drain control circuit to the drain diffused region, so as to accumulate a predetermined amount of charges of a predetermined conductivity type in an accumulation region, and the charges of a predetermined conductivity type accumulated in the accumulation region are discharged thereafter.

Abstract: Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.

Abstract: An electronic component includes a semiconductor chip which has an active upper side and a passive rear side. The semiconductor chip is surrounded by a sawn edge. This edge of semiconductor material has profile-sawn contours. The profile-sawn contours are surrounded by a plastics composition forming an edge of plastic. The plastics composition is in form-locking engagement with the profile-sawn contours. A method of producing a component of this type is also provided.

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

Abstract: A diamond ultraviolet luminescent element (10) having a current-injection light-emitting diode structure includes a high-quality boron-doped p-type diamond crystal (semiconductor layer) (1) synthesized by the high pressure and high temperature method; a phosphorous-doped n-type diamond crystal (n-type semiconductor layer) (3) formed on the first diamond surface by the chemical vapor deposition; an electrode (5) formed on the surface of the n-type semiconductor layer (3); and an electrode (7) formed on the surface of the p-type semiconductor layer (1). The luminescence (235 nm) attributed to the recombination of free excitons resulting from current injection dominates in ultraviolet wavelength region (10).

Abstract: A photon detector is obtained by using the intersubband absorption mechanism in a modulation doped quantum well(s). The modulation doping creates a very high electric field in the well which enables absorption of input TE polarized light and also conducts the carriers emitted from the well into the modulation doped layer from where they may recombine with carriers from the gate contact. Carriers are resupplied to the well by the generation of electrons across the energy gap of the quantum well material. The absorption is enhanced by the use of a resonant cavity in which the quantum well(s) are placed. The absorption and emission from the well creates a deficiency of charge in the quantum well proportional to the intensity of the input photon signal. The quantity of charge in the quantum well of each detector is converted to an output voltage by transferring the charge to the gate of an output amplifier.

Abstract: An optoelectronic device is disclosed. The optoelectronic device comprises a transparent conductive substrate, an optoelectronic element, and a base. The transparent conductive substrate comprises a transparent plate, a transparent electrode film formed on the transparent plate, and an insulating part formed on the transparent plate. The insulating part divides the transparent electrode film into a first transparent electrode film and a second transparent electrode film that non-conduct each other. The optoelectronic element comprising a positive electrode and a negative electrode is disposed on the transparent conductive substrate and electrically connected to the first transparent electrode film and the second transparent electrode film individually. The base is formed with an opening that has a reflective surface on the bottom of the opening, and the optoelectronic element is held in the opening in a manner of suspending from or connecting with the bottom of the opening.

Abstract: A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material. The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. The dielectric along the sidewalls of the trenches serves as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material.

Abstract: A bipolar device has at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide, wherein those portions of those stacking faults that grow under forward operation are segregated from at least one of the interfaces between the active region and the remainder of the device.

Abstract: In the light-emitting gallium-nitride-group compound semiconductor devices using a substrate, the operating voltage is lowered and at the same time the occurrence of crack during crystal growth is suppressed, resulting in an improved manufacturing yield rate. The device includes a stacked structure of an n-type layer, a light-emitting layer and a p-type layer formed in the foregoing order on a substrate, and an n-side electrode formed on the surface of the n-type layer. The n-type layer is a laminate layer composed of, in the order from the substrate, first n-type layer and a second n-type layer having a carrier concentration higher than that of the first n-type layer. As the contact resistance between the n-type layer and the n-side electrode formed thereon is reduced, the operating voltage of a light-emitting device is lowered, and the power consumption decreased.

Abstract: A semiconductor device includes a plurality of photoelectric conversion photodiodes provided on a silicon substrate, and a refractive index matching film provided on each of the photodiodes. The refractive index matching film is composed of an insulating compound layer represented by SiOxNy (0≦x and y) assuming that the molar ratio of silicon, oxygen and nitrogen of the compound layer is 1:x:y. The oxygen content of the compound layer is the lowest at the silicon interface with each photodiode and the highest in an upper portion of the compound layer, and the nitrogen content is the highest at the silicon interface with each photodiode and the lowest in the upper portion of the compound layer. Therefore, multiple reflection can be decreased to improve light receiving sensitivity, as compared with a case in which a SiN single layer and a SiO2 single layer are laminated.