Abstract: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Abstract: In accordance with the invention, the width of a gate electrode is smaller than the width of the semiconductor film. A sub gate electrode connected to the gate electrode is disposed, at the gate electrode side of the semiconductor film, away from the semiconductor film more than gate electrode. The width of the sub gate electrodes is larger than the width of the semiconductor film. Ends of the semiconductor film have regions formed of an intrinsic semiconductor which is not doped with dopant. In a semiconductor device, this structure is suitable to reduce degradation over time which is caused by an increase of the electric field strength or the carrier concentration at the ends of the semiconductor film.

Abstract: An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric thicknesses, but with different electrical gate dielectric thicknesses. The device undergoing multiple doping processes have different dopant concentrations, thereby providing different electrical characteristics such as the threshold voltages.

Abstract: A structural configuration and manufacture method is applied to manufacture electronic circuits on a ceramic substrate including capacitor and inductors for filters. The electronic circuits have strong bonding to securely adhere to the SOG-coated substrate when the SOG is cured at an elevated temperature supplemented with high nitrogen flow during the curing process. The SOG coated ceramic substrate shows excellent layer compatibilities during temperature variations because reduced differences of thermal coefficients between different layers.

Abstract: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

Abstract: The present invention provides a diffusion barrier useful in an integrated circuit, which serves to prevent the migration of material from a conductive layer to the underlying substrate and further provides improved adhesion of the conductive layer to the substrate. The diffusion barrier comprises a polymer which is a polyelectrolyte, having both cationic and anionic groups along its backbone chain. Preferred polyelectolyte barriers are polyethyleneimine (PEI) and polyacrylic acid (PAA). Other polyelectrolytes may be used, such as those that contain SH—OH— aromatic groups, or those that can interact with either the metal or the adjacent layers via covalent interactions and cross-linking (e.g., POMA, PSMA). The polymeric layer may be applied in two coatings, so that the amine side chains contact the dielectric (e.g. silicon) substrate and the acidic groups are adjacent to the overlying metallic interconnect (e.g. copper).

Abstract: A manufacturing method of a semiconductor device having a side wall insulating film, comprising; forming a gate insulating film on a semiconductor substrate, forming a gate electrode on the gate insulating film, forming a first side wall insulating film on a side surface of the gate electrode, forming a projecting portion on a first upper surface of the semiconductor substrate adjacent to the first side wall insulating film, forming a first diffusion layer by introducing impurities to the projecting portion formed on the semiconductor substrate, removing the first side wall insulating film so as to expose a second upper surface of the semiconductor substrate located below the first side wall insulating film, a width of the second upper surface exposed being a X, forming a second diffusion layer by introducing impurities to the second upper surface of the semiconductor substrate, and forming a second side wall insulating film on the side surface of the gate electrode and the second upper surface of the semicon

Abstract: A power semiconductor device of the trench variety in which the trenches follow a serpentine path.

Abstract: A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material. The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material. The trench isolation technique can be used to fabricate memory, logic and imager devices which can exhibit reduced current leakage and/or reduced optical cross-talk.

Abstract: A circuit array substrate is provided with thin-film transistors 4 and 5 and PIN diode 6 formed on insulation substrate 3. Active layer 11 and photo-electric sensor portion 21 are made of poly-silicon films. Impurities are doped into active layer 11 and photo-electric sensor portion 21 in the same process chamber, if necessary, to make their impurity concentrations different from each other. Thin-film transistors 4 and 5 with prescribed characteristics and PIN diode 6 with improved photosensitivity can be simultaneously, easily manufactured on insulation substrate 3 with a lesser number of processes.

Abstract: The invention achieves stable performance, such as low parasitic capacitance generated at conductive components. Components having a low dielectric constant of 4 or less are disposed on a base member. Functional films partitioned by the low-dielectric-constant components are also provided.

Abstract: A gate oxide film covering a light-incident surface of a photodiode includes an opening exposing a central region of the light-incident surface of the photodiode. After forming the opening in the gate oxide film serving as a light-incident surface protecting film, an antireflection film of silicon nitride, covering the light-incident surface of the photodiode is deposited. A side surface of the antireflection film is spaced from the field oxide film that is proximate the photodiode and that provides electrical isolation. Another side surface of the antireflection film faces a transfer gate of the device and is disposed on the gate oxide film near the opening. That side surface of the antireflection film is spaced from the transfer gate.

Abstract: A field effect transistor memory cell has a source region, a drain region, a channel region and a gate region, with the channel region extending from the source region to the drain region and being formed from at least one nanowire which has at least one defect such that charges can be trapped in the defects and released from the defects by a voltage applied to the gate region. A memory device built up from such memory cells and a method of manufacturing such memory cells is also disclosed.

Abstract: A light emitting diode of this invention comprises: a base substrate having a pair of electrode portions; a light emitting element mounted on the base substrate and electrically connected to the electrode portions; a reflection cup placed on the base substrate to surround the light emitting element; and a resin sealant sealing the light emitting element; wherein the base substrate is formed with a raised portion on an upper surface thereof and the light emitting element is placed on a top surface of the raised portion so that side surfaces of the light emitting element are situated higher than a lower end of the reflection cup. With this construction, light emitted from the side surfaces of the light emitting element can be extracted efficiently in an upward direction.

Abstract: A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate electrode, a first spacer which is formed in contact with the other side surface of the gate electrode, a second spacer which is formed in contact with the first offset-spacer, and source and drain regions which are formed apart from each other in the major surface of the semiconductor substrate below the first and second spacers so as to sandwich the gate electrode and the first offset-spacer. The source region is formed at a position deeper than the drain region. The dopant concentration of the source region is higher than that of the drain region.

Abstract: A thin film transistor and an active matrix flat panel device. By forming a conductive material layer having multiple profiles, critical dimension (CD) bias is reduced and step coverage is enhanced. The thin film transistor includes the conductive material layer formed on an insulating substrate, wherein the conductive material layer is composed of at least one thin film transistor conductive material layer, and an edge portion of the conductive material layer is composed of multiple profiles with multiple edge taper angles.

Abstract: A lateral channel transistor with an optimal conducting channel formed in widebandgap semiconductors like Silicon Carbide and Diamond is provided. Contrary to conventional vertical design of power transistors, a higher, optimum doping for a given thickness supports higher source/drain blocking voltage. A backside gate is insulated from the channel region using a low doped layer of the opposite conductivity type than the channel region to support the rated blocking voltage of the device.

Abstract: A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drain layer has a drain Fermi-Level (EF4). A channel layer is provided between the source layer and the drain layer, the channel layer being made with a material having a channel band-gap (EG3) and a channel mid-gap value (EGM3), the channel layer having a channel Fermi-Level (EF3). A source contact layer is connected to the source layer opposite the channel layer, the source contact layer having a source contact Fermi-Level (EF1). A gate electrode has a gate electrode Fermi-Level (EF6). The source band-gap is substantially narrower (EG2) than the channel band-gap (EG3).

Abstract: An integrated circuit includes a high voltage Schottky barrier diode and a low voltage device. The Schottky barrier diode includes a lightly doped p-well as guard ring while the low voltage devices are built using standard, more heavily doped p-wells. By using a process including a lightly doped p-well and a standard p-well, high voltage and low voltage devices can be integrated onto the same integrated circuit. In one embodiment, the lightly doped p-well and the standard p-well are formed by performing ion implantation using a first dose to form the lightly doped p-well, masking the lightly doped p-well, and performing ion implantation using a second dose to form the standard p-well. The second dose is the difference of the dopant concentrations of the lightly doped p-well and the standard p-well. In other embodiments, other high voltage devices can also be built by incorporating the lightly doped p-well structure.

Abstract: A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer to form a source region or a drain region; and sidewall-shaped control gates formed along both side surface of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other. The first control gate and the second control gate are respectively formed on insulating layers having different thickness.