Patents Examined by Gene M. Munson
  • Patent number: 7015542
    Abstract: A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer to form a source region or a drain region; and sidewall-shaped control gates formed along both side surface of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other. The first control gate and the second control gate are respectively formed on insulating layers having different thickness.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: March 21, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Yoshikazu Kasuya
  • Patent number: 7009226
    Abstract: Carrier mobility in transistor channel regions is increased by depositing a conformal stressed liner. Embodiments include forming a silicon oxynitride layer on the stressed liner to reduce or eliminate deposition surface pattern sensitivity during gap filling, and in-situ SACVD of silicon oxide gap fill directly on the stressed liner with reduced pattern sensitivity. Embodiments also include the use of Si—Ge substrates.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: March 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sey-Ping Sun
  • Patent number: 7005710
    Abstract: A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: February 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, David Kao
  • Patent number: 7005682
    Abstract: A semiconductor light emitting element of a monolithic structure, including: a first-conductivity-type semiconductor substrate; an active layer formed on the first-conductivity-type semiconductor substrate; a second-conductivity-type clad layer formed on the active layer; and a current diffusion layer formed on the second-conductivity-type clad layer, wherein the active layer is of a first conductivity type.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: February 28, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kiyohisa Ohta, Hiroshi Nakatsu, Kazuaki Sasaki, Junichi Nakamura
  • Patent number: 7005728
    Abstract: A substrate for use in an inline IC package is designed such that its die attach pad and leads each have a number of protrusions and recesses. These protrusions and recesses create an irregular surface that provides better adhesion to encapsulant material than conventional leads and die attach pads, whose smooth, straight surfaces risk delamination of the encapsulant material.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: February 28, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Felix C. Li
  • Patent number: 7002224
    Abstract: A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal processes used to manufacture the transistor, dopant species from the doped region of the workpiece are outdiffused into the gate dielectric, creating a doped gate dielectric. The dopant species fill vacancies in the atomic structure of the gate dielectric, resulting in a transistor having increased speed, reduced power consumption, and improved voltage stability.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: February 21, 2006
    Assignee: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Patent number: 7002184
    Abstract: In the light-emitting gallium-nitride-group compound semiconductor devices using a substrate, the operating voltage is lowered and at the same time the occurrence of crack during crystal growth is suppressed, resulting in an improved manufacturing yield rate. The device includes a stacked structure of an n-type layer, a light-emitting layer and a p-type layer formed in the foregoing order on a substrate, and an n-side electrode formed on the surface of the n-type layer. The n-type layer is a laminate layer composed of, in the order from the substrate, first n-type layer and a second n-type layer having a carrier concentration higher than that of the first n-type layer. As the contact resistance between the n-type layer and the n-side electrode formed thereon is reduced, the operating voltage of a light-emitting device is lowered, and the power consumption decreased.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: February 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunari Oku, Hidenori Kamei
  • Patent number: 7002216
    Abstract: Disclosed are architectures and method for semiconductor ESD protection using grouped diodes, with the diode groups being electrically separated by substrate resistance. The mixed diode/resistor groups are arranged to be in an off state under normal operating conditions and to discharge ESD current between power lines. The disclosed architectures and method protects circuits using different power supplies and/or voltage inputs.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: February 21, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shao-Chang Huang
  • Patent number: 6998659
    Abstract: A solid state image sensor has an array of pixels formed on an epitaxial layer on a substrate. Each pixel is relatively large so that it has a high light collecting ability, such as 40–60 ?m, but the pixel photodiode is relatively small so that it has a low capacitance, such as 4–6 ?m. Active elements of the pixel photodiode are formed in wells that are spaced away from the pixel photodiode so that the latter is surrounded by epitaxial material.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: February 14, 2006
    Assignee: STMicroelectronics Ltd.
    Inventor: Jeff Raynor
  • Patent number: 6989578
    Abstract: An inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type and at least two deep wells of opposite conductivity type in the substrate underneath the track. In another embodiment, an inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type; a shallow trench isolation region formed in the substrate underneath the trace; and at least two deep wells of opposite conductivity type in the substrate underneath the shallow trench isolation region. The present invention also includes methods of manufacturing the aforementioned inductors.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: January 24, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tzu-Jin Yeh, Hsien-Chang Wu, Ming-Ta Yang, Yu-Tai Chia
  • Patent number: 6989570
    Abstract: A transistor is located on a base layer 1 resting on a semiconductor substrate SB and formed from a relaxed silicon-germanium layer, and includes, under the isolated gate 7, a first strained silicon layer 2 resting on the base layer 1, surmounted by a buried insulating layer 10, surmounted by a second strained silicon layer 4 extending between the source S and drain D regions.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: January 24, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Daniel Bensahel
  • Patent number: 6984864
    Abstract: In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si for the barrier film increasing the contact resistance to n-Si and backwardly biasing the emitter and base of a parasitic bipolar transistor making it less tending to turn-on, thereby decreasing the leak current of power MISFET.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: January 10, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Tomoaki Uno, Yoshito Nakazawa
  • Patent number: 6982454
    Abstract: A capacitor includes a semiconductor substrate, a bottom conductive pattern, first to third insulating layers, first to third metal plates and a connecting pattern. The bottom conductive pattern is formed on the semiconductor substrate. The first to third insulating layers are formed on the bottom conductive pattern, the first and second metal plates, respectively. The first metal plate is formed on the first insulating layer within a first area. The first metal plate is electrically connected to the bottom conductive pattern. The second metal plate is formed on the second insulating layer within the first area. The second metal plate has an opening in the center thereof. The third metal plate is formed on the third insulating layer. The connecting pattern is formed through the second and third insulating layers and the opening of the second metal plate. The connecting pattern electrically connects the first and the third metal plate.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: January 3, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Horia Giuroiu, Sorin Andrei Spanoche
  • Patent number: 6982465
    Abstract: The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30, a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: January 3, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yukihiro Kumagai, Hiroyuki Ohta, Fumio Ootsuka, Shuji Ikeda, Takahiro Onai, Hideo Miura, Katsuhiko Ichinose, Toshifumi Takeda
  • Patent number: 6975003
    Abstract: An N-channel transistor includes: an N-type source region, a gate electrode, a P-type body region, an N-type drain offset region, and a drain contact region, which is an N-type drain region. The transistor further includes a gate insulating film that has a thin oxide silicon film (a thin film portion) and a LOCOS film (a thick film portion). The body region has an impurity profile in which the concentration reaches a maximum value near the surface and decreases with distance from the surface. The drain offset region has an impurity profile that has an impurity-concentration peak in a deep portion located a certain depth-extent below the lower face of the LOCOS film.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: December 13, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Osamu Matsui, Yoshinobu Sato
  • Patent number: 6974977
    Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: December 13, 2005
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Katsuyoshi Washio, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Katsuya Oda, Eiji Oue, Masamichi Tanabe
  • Patent number: 6975029
    Abstract: Disclosed is an inexpensive semiconductor device which has a built-in antenna capable of efficiently radiating low-power microwaves and has excellent productivity. An IC chip is mounted on a lead frame on which a chip base for mounting an IC chip, an inverted-F antenna and a ground electrode are integrated and is molded with an encapsulating resin. At this time, a gap portion, which is formed between the open end of the resonance portion of the inverted-F antenna and the distal end portion of the ground electrode, is not molded with the encapsulating resin and is left open as a window. This can permit electric waves to be efficiently irradiated from the open end of the antenna exposed to air through the window. As this semiconductor device has nearly the same structure as that of an ordinary semiconductor device, it is excellent in productivity and can be fabricated at a low cost.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: December 13, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kimito Horie
  • Patent number: 6960784
    Abstract: A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a charging-sensitive insulator layer and complementary elements designed to effectively provide an indicative potential drop across the charging sensitive insulator.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: November 1, 2005
    Assignee: Intel Corporation
    Inventors: Wallace W. Lin, George E. Sery
  • Patent number: 6960782
    Abstract: Described is an electronic device comprising a junction formed between a first fullerene layer having a first doping concentration and a second fullerene layer having a second doping concentration different from the first doping concentration. The first doping concentration may be zero. The first and/or the second fullerene layer may be a monolayer. The second fullerene layer may comprise an electron donor. One example of such a device is a diode wherein the first fullerene layer is connected to an anode and the second fullerene layer is connected to a cathode. Another example is a field effect transistor wherein the first fullerene layer serves as a gate region and the second fullerene layer serves as a channel region. The second fullerene layer may alternatively comprise an electron acceptor. At least one of the first and second fullerene layers may be formed from C60, or may consist of a single bucky ball.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: November 1, 2005
    Assignee: International Business Machines Corporation
    Inventors: Rolf Allenspach, Urs T. Duerig, Walter Riess, Reto Schlittler
  • Patent number: 6960799
    Abstract: An array of photodiodes includes regions of a second conductivity type formed in a semiconductive region of a first conductivity type, divided into three interleaved sub-arrays. All the photodiodes of a same sub-array are coated with a same interference filter including at least one insulating layer of determined thickness coated with at least one conductive layer. According to the present invention, the conductive layers are electrically connected to the semiconductive region of a first conductivity type.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: November 1, 2005
    Assignee: STMicroelectronics A.A.
    Inventor: Pierrick Descure