Abstract: To provide a super high-speed heterojunction bipolar transistor, a semiconductor device including such a heterojunction bipolar transistor has a structure wherein a subcollector layer, collector layer, base layer, emitter layer (InGaP layer) and emitter cap layer are successively formed in predetermined shapes a surface of a semi-insulating GaAs substrate, an inner edge part of a base electrode overlaps a periphery of the emitter layer, and the base electrode is electrically connected to the base layer by an alloy layer formed by alloying the emitter layer under the base electrode. The emitter layer is selectively formed on the base layer. The base electrode extends from the peripheral part of the emitter layer across the base layer, and the alloy layer extends to a midway depth of the base layer. The edge of the base layer is situated further inside than the outer edge of the base electrode.

Abstract: A self-aligned metal electrode sensor structure. The self-aligned metal electrode sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A sensor is formed adjacent to the interconnect structure. The sensor includes a pixel metallization section and a doped layer electrode. The pixel metallization section is electrically connected to the interconnect via. The pixel metallization section includes an outer surface which is substantially planar. The doped layer electrode includes an inner surface adjacent to the outer surface of the pixel metallization section. The entire inner surface of the doped layer electrode is substantially planar. A transparent conductive layer is formed adjacent to the sensor. The interconnect via and the transparent conductive layer electrically connect the electronic circuitry to the sensor.

Abstract: A wire in a semiconductor device and the fabricating the same are disclosed in the present invention. A semiconductor device includes a semiconductor substrate, a plurality of conductive layers on the semiconductor substrate, and an insulating layer on the semiconductor substrate including the conductive layers, the insulating layer having at least one void between each adjacent conductive layer.

Abstract: A back thinned CCD has at least first and second parallel n− signal channel segments and a p++ channel stop region between the signal channels.

Abstract: A charge coupled device has an n-type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p-type local impurity region is formed in such a manner as to form a p-n junction together with the n-type charge accumulating layer and the n-type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.

Abstract: The invention relates to a semiconductor device comprising a bipolar transistor having a collector (1), a base (2) and an emitter (3) at its active area (A). The semiconductor body (10) of the device is covered with an insulating layer (20). At least a part of a base connection conductor (5) and an emitter connection conductor (6) extend over the insulating layer (20) and lead to a base connection area (8) and an emitter connection area (9), respectively. The known transistor is characterized by poor gain, particularly at high frequencies and at high power.

Abstract: A CMOS sensor. The CMOS sensor comprises a substrate, a gate electrode formed on the substrate, a source/drain region formed in the substrate on one side of the gate electrode, and a sensor region formed in the substrate on another side of the gate electrode. The impurity in the source/drain region is arsenic. The source/drain further comprises a lightly doped drain region. The sensor region comprises a first doped region and a second doped region which together have a dentoid profile. The impurity in the first doped region and the second doped region is phosphorus.

Abstract: A charge-coupled device (CCD) image sensor that preserves defect gettering characteristics having a vertical overflow drain (VOD) for blooming protection is provided in a structure that provides low voltage electronic shuttering. This structure reduces the electronic shutter voltage to ease the demands on off-chip support circuitry required to operate the CCD image sensor. The invention provides an improved pixel structure to reduce this voltage. Prior art difficulties are avoided by providing uniform, n-type layers of varying doping levels underneath the entire area of the CCD device. Combined with a lightly doped n-type substrate these layers provide low voltage electronic shutter operation.

Abstract: A semiconductor device (102) having a plurality of diodes (100) with alterable electrical conductivity by a source of energy (30), e.g., a laser, external to the semiconductor device. The diodes are formed and energy is applied to alter the electrical conductivity at least 10%, and preferably by several orders of magnitude. Certain embodiments (20, 40 and 50) are formed so as to function as anti-fuses, while another embodiment (60) functions as a fuse. The diodes may be formed as planar diodes (20, 40, 50 and 60) or as lateral diodes (70).

Abstract: Robust alignment marks which are substantially resistant to degradation caused by semiconductor device fabrication steps are disclosed. The new alignment marks use a series of geometrical shapes that are staggered in respect to each other to achieve more left and right edges providing a checkerboard alignment mark. The geometrical shapes have a size that is selected so as to be within the resolving capability of the exposure tool, yet smaller than the resolving capability of the alignment system. The small staggered geometrical shapes provide a more symmetrical signal which is more resistant to variability in prior processing steps than the standard mark design.

Abstract: An Metal Insulator Metal (MIM) capacitor having improved performance in a high frequency range. The MIM capacitor comprises: a lower electrode; a second insulating film formed on the lower electrode; a capacitor insulating film formed on a portion of the lower electrode; an upper electrode formed on the capacitor insulating film; a third insulating film formed on the second insulating film and the upper electrode; a first lead electrode which connects to a portion of the lower electrode; a second lead electrode which connects to a portion of the upper electrode. The first lead electrode is continuously formed such that the first electrode surrounds at least three sides of the capacitor insulating film, and the width H of the capacitor insulating film and maximum frequency F satisfy the formula: H<(A/F)½, where, A is a predetermined constant determined depending on a structure and manufacturing process of the MIM capacitor to obtain desired admittance characteristics.

Abstract: A field-programmable gate array of the present invention includes a program element for connecting/disconnecting first and second basic cells to/from each other responsive to a program externally input and for storing thereon the connection or disconnection state between the first and second cells. The program element includes: a switching device implemented as a CMOS circuit; and a nonvolatile memory device, which stores thereon the ON/OFF states of the switching device and includes a lower electrode, a capacitive insulating film made of a ferroelectric thin film, and an upper electrode. A first interlevel insulating film is formed over the switching device. And a buffer layer for matching a lattice constant of the first interlevel insulating film with that of the ferroelectric thin film is formed on the first interlevel insulating film.

Abstract: A photoelectric conversion integrated circuit device for converting a light signal into a voltage signal has a photodiode that outputs a current in accordance with a light signal it receives, a current-to-voltage conversion circuit that outputs a voltage signal in accordance with a current signal it receives, and a test circuit that outputs a current and whose on/off state is controllable from the outside. At the output of the photodiode, two output terminals are provided, of which one is connected to the current-to-voltage conversion circuit and the other to the test circuit. This photoelectric conversion integrated circuit device allows a fault in the wiring between the photodiode and the current-to-voltage conversion circuit to be detected by feeding an input current to the current-to-voltage conversion circuit without shining light on the photodiode.

Abstract: A field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.

Abstract: A vertical channel flash memory cell with a silicon germanium layer in the channel region provides enhanced secondary electron injection when programming the device. The device includes a silicon substrate, a silicon germanium alloy layer epitaxially grown on the substrate, and a silicon layer epitaxially grown on the silicon germanium layer. A sidewall through the stacked structure is formed by etching thereby exposing edges of the silicon layer and the silicon germanium layer and a portion of the substrate. A floating gate is formed overlying the sidewall and insulated therefrom with a control gate overlying the floating gate and insulated therefrom. A source region is formed in the silicon layer and a drain region is formed in the substrate with a channel therebetween along the sidewall and including the silicon germanium layer. The silicon germanium layer is preferably compressively strained and can have a uniform mole fraction or a graded mole fraction.

Abstract: A metal nitride oxide semiconductor (MNOS) type memory using a threshold voltage variation (&Dgr;Vth) due to charging of a single electron when the width of a channel of the memory is set to be smaller than or equal to the Debye screen length (LD) of an electron, and a driving method thereof, are provided. The MNOS memory uses a threshold voltage variation (&Dgr;Vth) due to charging of a single electron occurring when the width of a channel is set to be smaller than or equal to the Debye screen length (LD) which depends on the impurity concentration of a semiconductor substrate.

Abstract: A bipolar transistor having at least a low doped drift layer (14) of crystalline SiC comprises at least one first layer (13) of a semi-conductor material having a wider energy gap between the conduction band and the valence band than an adjacent layer (14) of SiC.

Abstract: A charge transferring device includes a detection MOSFET for detecting a signal charge, a reset MOSFET for removing the signal charge after the signal charge is detected. The reset MOSFET includes a floating diffusion layer to which the signal charge is transferred, an impurity layer to which a reset voltage is applied, and a reset gate electrode to which a reset signal is supplied. The detection MOSFET includes a detection gate electrode connected with the floating diffusion layer. The floating diffusion layer includes a first semiconductor region and a second semiconductor region whose impurity concentration is lower than that of the first semiconductor region. The impurity concentration of the first semiconductor region is set to a concentration such that the first semiconductor region is not depleted in a voltage lower than the reset voltage when the reset signal is supplied to the reset gate electrode.

Abstract: A semiconductor photo-detector, which has a high quantum efficiency due to high coupling with an incident beam and operates at higher frequency due to a reduced area of PN junction. In a semiconductor photo-detector of the present invention, reflection layers are deposited on both of the parallel surfaces of a square-shaped wave-guide, while light absorption layers are deposited on at least another pair of parallel surfaces which is one of the parallel pairs of remaining surfaces.

Abstract: A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of