Abstract: A semiconductor device includes a first interlayer film of SiN and a second interlayer film of SiO2 that are formed in the order over a semiconductor substrate having, at a surface, a conductive layer. In the same or different etching process, a contact or via hole is formed through the first interlayer film above the conductive layer, while an interconnect trench is formed through the second interlayer film.

Abstract: A pinned photodiode is operated without a transfer gate. This is done by forming a pinned photodiode which has a selective connection to the substrate. When the connection is turned on, the photodiode is pinned to the substrate, and kept at a specified potential. When the connection is off, the photodiode is disconnected from the substrate and hence floats. In this way, the area above the photoreceptor can be used both for a reception area and for a charge transfer area.

Abstract: A light guide plate, surface light source device and liquid crystal display of a double-reflection-direction-conversion type have a heightened applicability to an front-lighting arrangement. A back face 14 of a light guide plate 10 is provided with micro-reflectors shaped like trapezoids each of which has a bottom face extending generally in parallel with a general plane of the back face 14. A main input light H10 to a micro-reflector 20 is incident to an incidence end face 12 (at point a) and inputted thereto in a somewhat downward inclined direction. An inner input light is inner-reflected mainly by slopes 21 and 22 successively (at points b and c), becoming an inner output light IO directed to an emission face 13. The inner output light IO is emitted from the emission face 13 (at point d), being supplied to an LCD panel or the like after transmitting through a light diffusion sheet DF (points e and f).

Abstract: A method for fabricating a semiconductor device and a semiconductor formed by this method, the method including, the steps of sequentially forming a pad oxide film, a polysilicon film, and an antioxidation film on an active region of a semiconductor substrate such that a field region is exposed; etching an exposed portion of the surface of the substrate to a predetermined thickness to form a trench within the substrate; forming a first insulation film along the inner face of the trench by using an oxidation process; forming a stress buffer film on the entire surface of the resultant structure; forming a second insulation film on the stress buffer film such that the trench is sufficiently filled; making the second insulation film planar such that the remaining antioxidation film has a predetermined thickness on the active region of the substrate so as to form a shallow trench isolation within the trench; and sequentially removing the remaining antioxidation film, the polysilicon film, and the pad oxide film.

Abstract: A MOS control diode is provided for power switching. In the MOS control diode, a switching speed is high and a reverse leakage current characteristic is improved without additionally needing processes for improving reverse recovery time by converting a power MOSFET which is a majority carrier device to diode having two terminals. Such a MOS control diode can be achieved by forming a discontinuous area in a gate oxide film formed on the surface of a semiconductor substrate so that the conductive gate electrode is connected to the semiconductor substrate. Also, it is possible to form a trench in the semiconductor substrate, to form the gate oxide films on the sidewall of a trench, and to connect the gate electrode to the semiconductor substrate through the bottom of the trench.

Abstract: A semiconductor light emitting element includes: a first conductive type layer made of a nitride semiconductor which is deposited on a substrate; a quantum well active layer made of AlPGaQIn1−P−QN (O≦P, O≦Q, P+Q<1) which is deposited on the first conductive type layer, the quantum well active layer including a pair of barrier layers and a well layer interposed therebetween; and a second conductive type layer made of a nitride semiconductor which is deposited on the quantum well active layer, wherein light spontaneously emitted from end faces of the quantum well active layer to polarized in a direction parallel to the substrate.

Abstract: In a ferroelectric data processing device for processing and/or storage of data with passive or electrical addressing a data-carrying medium is used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched between these and is provided as a continuous layer in or adjacent toelectrode structures in the form of a matrix. A logic element (4) is formed at the intersection between an x electrode (2) and a y electrode (3) of the electrode matrix. The logic element (4) is addressed by applying to the electrodes (2, 3) a voltage greater than the coercivity field of the ferroelectric material.

Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.

Abstract: A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.

Abstract: A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling ions such as carbon are implanted into all contacts of the substrate. High resistive contacts are temporarily covered with an oxide during processing to prevent silicide from forming due to interaction between a siliciding metal and the implanted mobility spoiling ions in the contacts. The resulting high resistance contacts have highly linear I-V curves, even at high voltages. Selective silicide formation converts some of the contacts back to low resistance contacts as a result of interaction between a siliciding metal and the implanted mobility spoiling ions in the low resistance contacts.

Abstract: A semiconductor device having a semiconductor resistance element is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration which is difficult to control, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a donor concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract: A photodiode and a read gate are formed within an element region. A p+ type punch-through preventing region is not formed immediately under an n-type signal accumulating region of a photodiode. The n-type signal accumulating region is formed within a p-type semiconductor substrate. The p+ type punch-through preventing region is formed over the entire element region. The p+ type punch-through preventing region is also formed immediately under an insulative isolation layer in order to prevent punch-through between elements. A p+ type punch-through stopper is formed immediately under an n-type first semiconductor region.

Abstract: A semiconductor infrared detector includes in the following order: a semiconductor substrate; a layer of electrically insulating material; and patterns formed in a semiconductor layer. The patterns are formed from at least one island that is connected to bridges which are connected to polarization electrodes. The bridges are lines having an approximately constant width lp and the islands are zones having a width li that is greater than that of the lines.

Abstract: Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.

Abstract: A capacitive structure including single crystal silicon and an insulating layer in a semiconductor substrate. One embodiment of the present invention includes an optical switching device having one or more capacitive structures including single crystal silicon in a substrate such as a silicon-on-insulator (SOI) wafer and can be used in a variety of high bandwidth applications including multi-processor, telecommunications, networking or the like. In one embodiment, a capacitive structure includes single crystal silicon disposed in a first semiconductor material with an insulating layer disposed between the single crystal silicon and the semiconductor material. In one embodiment, a capacitive structure may be formed by laterally growing single crystal silicon through an opening in a trench adjacent to a trench where the capacitive structures is formed.

Abstract: To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.

Abstract: A method of forming a bump structure, comprising the following steps. A structure having an exposed first conductive structure is provided. A first photoresist layer is formed over the structure and the exposed first conductive structure. A second capping photoresist layer is formed over the first photoresist layer. The first and second photoresist layers being comprised of different photoresist materials. The first and second photoresist layers are patterned to form an opening through the first and second photoresist layers and over the first conductive structure. The second capping photoresist layer prevents excessive formation of first photoresist layer residue during processing. A second conductive structure is formed within the opening. The first and second patterned photoresist layers are stripped. The second conductive structure is reflowed to form the bump structure.

Abstract: The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory material. The second side has a length that is less than the first side. Additionally, a second dielectric may overlie the lower electrode. The second dielectric has a shape that is substantially similar to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes providing a lower electrode material in a recess. The method also includes removing at least a portion of the second side.

Abstract: A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor on the conductive channel of the first type, depositing an FEM capacitor over less than the entire area of the MOS capacitor, thereby forming a stacked gate unit, implanting doping impurities of a second type in the silicon substrate on either side of the gate junction region to form a conductive channel of a second type for use as a source junction region and a drain junction region, and depositing an insulating structure about the FEM gate unit.