Abstract: A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive track extending above the substrate between the second region and the wall. The component includes a succession of trenches extending in the substrate under the track and perpendicularly to this track, each trench being filled with an insulator.

Abstract: The invention relates to a semiconductor device, in particular a Schottky hybrid diode with a guard ring (S). The semiconductor device comprises a semiconductor substrate (1), an epitaxial layer (2) on which an insulating layer (3) with an opening (10) is deposited, with a Schottky metal layer (9) covering the epitaxial layer (2) lying at the bottom of the opening (10), and with an annular semiconductor region (4) which is present in the epitaxial layer (2). A doping region (6) is present in the epitaxial layer (2) along the outer contour of the semiconductor device, and in addition an oxide layer (8) is present on the epitaxial layer (2).

Abstract: Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure upon a conductor stud layer formed into a first via defined by a patterned dielectric layer to reach a one of a pair of patterned conductor layers within the microelectronic fabrication prior to forming through the patterned dielectric layer a second via to reach the other of the pair of patterned conductor layers within the microelectronic fabrication. The method provides the resulting microelectronic fabrication with enhanced reliability and performance.

Abstract: A Zener diode is provided in a chip periphery portion which entirely surrounds at a periphery a unit cell portion and a gate pad portion along first to fourth directions. The Zener diode has an N+-P-N+-P-N+ structure consisting of an N+ type layer, a P type layer, an N+ type layer, a P type layer, and an N+ type layer, in which these layers extend along the first to fourth directions. With this structure, a power semiconductor device achieves a higher electrostatic strength by (1) a reduction in on-state resistance through enlargement of an effective cell region by downsizing the gate pad, and (2) an improvement in current-voltage characteristic of the Zener diode through an increase in PN junction width.

Abstract: The invention concerns the use of spin-on-glass (SOG) to bond two layers of semiconductor together, in order to form a Silicon-on-Insulator (SOI) structure. One type of SOG is a cross-linked siloxane polymer, preferably of the poly-organo-siloxane type, comprising a carbon content of at least 5 atomic weight percent.

Abstract: A thin-film semiconductor device which has a pixel array section and a peripheral circuit section arranged around it, said pixel array section containing pixel electrodes and thin-film transistors for pixels which switch the pixel electrodes, said peripheral circuit section containing driving circuits each having thin-film transistors for circuits which drive the thin-film transistors for pixels, said each thin-film transistor having the laminate structure having a semiconductor thin film, a gate electrode, and a gate insulating film interposed between them, and said semiconductor thin film having a channel region inside the end of the gate electrode, a lightly doped region outside said channel region, a heavily doped region outside said lightly doped region, and a concentration boundary which separates said lightly doped region and heavily doped region from each other, wherein said concentration boundary measured from the end of said gate electrode is positioned more inside in said thin-film transistor for c

Abstract: A semiconductor body has source and drain regions (4 and 5) spaced apart by a body region (6) and both meeting a surface (3a) of the semiconductor body. A gate structure (7) is provided within a trench (8) for controlling a conduction channel in a conduction channel accommodation portion (60) of the body region (6) extending along at least side walls (8a) of the trench (8) and between the source and drain regions (4 and 5). A voltage-sustaining zone (600) consisting of first regions (6) of the same conductivity type as the source and drain regions interposed with second regions (62) of the opposite conductivity type is provided such that the first regions (61) provide a path for majority charge carriers to the drain region (5) when the device is conducting.

Abstract: A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer.

Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: A semiconductor device of a pin junction structure, constituted by a quantum-wave interference layers Q1 to Q4 with plural periods of a pair of a first layer W and a second layer B and middle layers (carrier accumulation layers) C1 to C3. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of wavelength of quantum-wave of carriers conducted in the i-layer in each of the first layer W and the second layer B existing at the level near the lowest energy level of the second layer B. A &dgr; layer, for sharply varying energy band, is formed at an every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. Then quantum-wave interference layers and carrier accumulation layers are formed in series.

Abstract: A liquid crystal display panel includes a gate line and a signal line intersecting the gate line at an intersection portion where the gate line and the signal line intersect each other. The gate line includes at least two conductive portions and at least one opening portion on the intersection portion. The at least one opening portion on the gate line is used for removing an etching stopper layer.

Abstract: A power transistor cell includes an air bridge and a plurality of individual transistors. Each of the plurality of individual transistors has at least one separate connection contact. Each of the at least one separate connection contact of the plurality of individual transistors is thermally conductively connected to one another through the air bridge forming air bridge connections, which define a contact plane. A surface of the contact plane that contains each connection path between two of the air bridge connections defines a convex region. The air bridge is formed to have, in the contact plane, dimensions that exceed a smallest convex region containing all of the air bridge connections in all directions of the air bridge. Each of the plurality of power transistor cells can be respectively thermally conductively connected to one another through the air bridge to form a block of power transistor cells.

Abstract: A memory device including at least one pair of spaced apart conductors and a ferroelectric material between the pair of conductors. The pair of conductors is spaced apart a distance sufficient to permit a tunneling current therebetween.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

Abstract: An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and the highly doped layer is doped with the same type of dopant as the buried collector, but to a lower concentration. The sub-layer causes a more even distribution of the potential lines in the substrate and in a sub-collector layer, thereby eliminating areas of dense potential lines and increasing the breakdown voltage of the component, (i.e., because the breakdown voltage is lower in areas with dense potential lines).

Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.