Abstract: The invention relates to an electrically erasable, non-volatile memory device, having a memory cell of the floating gate type (16), defined by a source zone, a drain zone, a channel zone (8) and a control gate zone (6), the latter being separated from the channel zone by an insulation zone (14), said five zones being implemented in a semiconductor film formed on an insulating layer (4), said memory cell being laterally insulated by one or more insulation zones (10, 12) in contact with the insulating layer.

Abstract: A discharge circuit for pulsed laser 10 in which one connecting portion of a preionization capacitor Cpp is connected to a preionization electrode 4 and the other one connecting portion of the preionization capacitor Cpp is connected to a junction between a capacitor C2 and a magnetic switch AL2. In the discharge circuit for pulsed laser 10, a voltage Vcc of the preionization capacitor Cpp, which is charged in synchronization with the charging of the capacitor C2, increases at a time t3 earlier by a predetermined time than a start time t6 of main discharge by the main discharge electrodes 1, 2. When a voltage of the preionization electrode 4 increases to a predetermined preionization start voltage through the preionization capacitor Cpp, a main discharge gap 3 is preionized by a corona discharge caused by the preionization electrode 4 and the main discharge is caused by the main discharge electrodes 1, 2 with the main discharge gap 3 fully preionized.

Abstract: An integrated circuit can include gate structures designed to effect a work function of a transistor. A first set of gate structures can have a first work function and a second set of gate structures can have a second work function. The gate structures include metal layers to affect changes in the work function. The work function can affect the threshold voltage associated with the transistors. The transistor can be built on a silicon-on-insulator substrate.

Abstract: A semiconductor photodetection device includes a semiconductor structure including an optical absorption layer having a photo-incidence surface on a first side thereof, a dielectric reflecting layer formed on a second side of the semiconductor structure opposite to the first side, a contact electrode surrounding the dielectric reflecting layer and contacting with the semiconductor structure, and a close contact electrode covering the dielectric reflecting layer and contacting with the contact electrode and the dielectric reflecting layer, wherein the close contact electrode adheres to the dielectric reflecting layer more strongly than to the contact electrode.

Abstract: A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising: a metallization-line; a liner separating the metallization line and a combination Cu-alloy seed layer and a pure Cu layer; a dielectric surrounding the liner; and a dielectric cap disposed over the surrounding dielectric, the liner and the combination Cu-alloy seed layer and pure Cu layer; the laser fuse being characterized after Laser energizing by passivation areas: a) on the open Cu-fuse surface; and b) in the interfaces between: (i) the Cu-alloy seed layer and the liners and dielectric; and (ii) between the pure Cu layer and the dielectric cap.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: A semiconductor device may include an element isolation region 14, an npn-type bipolar transistor 200, and a p-type field effect transistor 100, which are formed on a SOI substrate. The bi-polar transistor 200 and the field effect transistor 100 are formed in the same element forming region 16. An n-type body region 52a is electrically connected to an n-type collector region 230. A p-type source region 210 is electrically connected to the n-type collector region 230. A p-type drain region 130 is electrically connected to a p-type base region 220.

Abstract: The present invention discloses a method of manufacturing an active matrix display device, comprising: a) forming a semiconductor layer on an insulating substrate; b) forming a gate insulating layer over the whole surface of the substrate while convering the semiconductor layer; c) forming a gate electrode on the gate insulating layer over the semiconductor layer; d) forming spacers on both side wall portions of the gate electrode while exposing both end portions of the semiconductor layer; e) ion-implaing a high-density impurity into the semiconductor layer to form high-density source and drain regions in the semiconductor layer; f) depositing sequentially a transparent conductive layer and a metal layer on the inter insulating layer; g) patterning the transparent conductive layer and the metal layer to form the source and drain electrodes, the source and drain electrodes directly contacting the high-density source and drain regions and having a dual-layered structure; h) forming a passivation layer over the

Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

Abstract: An apparatus and method for face-down connection of a die to a substrate with polymer electrodes, the method comprising forming a plurality of conductive polymer electrodes on a substrate assembly: and elevating the temperature of the die sufficiently to cause electrical and fixed connection of the die to the electrodes upon appropriate contact; and then bringing the die face and electrodes into appropriate contact thereby forming the fixed and electrical connection.

Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Abstract: The non-contact data carrier has a resin substrate, a metallic antenna coil on the resin substrate, and an IC chip connected to the antenna coil via a plurality of bumps. Each bump of the IC chip has a base on the side of the IC chip body of the data carrier and a projection held by the base via a shoulder. Each bump is connected to the antenna coil by piercing the projection into the antenna coil.

Abstract: A fuse structure. A first dielectric layer is formed on a substrate, a first conductive layer is formed on part of the first dielectric layer, a second dielectric layer is formed on part of the first dielectric layer and part of the first conductive layer, and a second conductive layer is formed on part of the second dielectric layer. A third dielectric layer is formed on part of the second conductive layer and part of the second dielectric layer, with an opening to expose part of the second conductive layer, to be defined as the laser spot position. A third conductive layer is formed on the third dielectric layer, with at least one conductive plug penetrating the second dielectric layer, to electrically connect the first conductive layer and the second conductive layer, to function as a fuse. Thus, in the present invention, the fuse structure of the third conductive layer can avoid damage to the adjacent fuse structure from the laser blow process.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap.

Abstract: A FRAM having a ferroelectric capacitor comprises a cylindrical type bottom electrode. A ferroelectric film is thinly stacked over the bottom electrode, and the first portion of the top electrode formed over and conformal to the ferroelectric film. A void that is left between sidewalls of the first portion of the electrode over the ferroelectric film is then filled with fill material for a fill layer. The fill material of the fill layer is then planarized to be level with and expose an upper surface of the first portion of the top electrode. A second portion of the top electrode is then formed over the fill layer and in contact with the exposed, e.g. peripheral regions of the first portion of the electrode. The fill material of the fill layer may be formed of polysilicon, silicon oxide or other material such as another metal.

Abstract: In an accelerometer, the stress is detected through electric amplification with the use of detecting elements 411-434 having an amplification function arranged on beams 3 and, with the use of a differential amplifier circuits 510 formed on the support base 1, an acceleration component in a detection axis direction to which the stress is applied is outputted as the differential mode and acceleration components in the other axis directions are outputted as the common mode, so that each axis sensitivity ratio between the detection axis sensitivity and the other axis sensitivities is enhanced largely.

Abstract: An access cell for routing current from a first cell to a second cell includes a first current path coupled to a second current path via a third current path. The third current path includes a set of three legs configured in a manner such that a first of the three legs may be severed in half to interrupt current flow between the first current path and the second current path, leaving the other two legs of the third current path intact. Either half of the first leg includes a connection point at which a spare cell may be coupled to the access cell to enable current flow between the spare cell and either the first cell or the second cell.

Abstract: A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap.