Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: A MOSFET transistor having silicide formed on top of a polysilicon gate conductor, on partially exposed sidewalls of the polysilicon gate conductor, and on junction regions in an underlying semiconductor substrate is provided. Opposed sidewalls of the polysilicon gate conductor are surrounded by dielectric sidewall spacers. An upper surface of the dielectric spacers is lower than an upper surface of the polysilicon gate conductor thereby exposing a portion of the sidewall surfaces of the polysilicon gate conductor. A substantial portion of the polysilicon gate conductor, including the top of the gate and the exposed portion of the sidewall surfaces, may then be subjected to a salicidation process. During this process, salicide structures are also formed on the junctions regions. Therefore, silicide may be simultaneously formed on a substantial portion of the polysilicon gate and on junctions regions providing a gate with lower resistivity without consuming the junction regions during salicidation.

Abstract: The present invention provide an LDD type TFT having excellent properties, particularly for a liquid crystal display unit. For this purpose, a top gate type LDDTFT gate electrode is converted into a two-stage structure by use of a chemical reaction or plating, and furthermore, into a shape in which an upper portion or a lower portion slightly protrudes on the source electrode side, or the drain electrode side relative to the other portions. Impurities are injected by using this electrode having this structure and shape as a mask. Prior to injection of impurities, the gate insulating film is removed, and a Ti film is formed for preventing hydrogen for dilution from coming in. This is also the case with the LDD-TFT on the bottom gate side.

Abstract: An electrical assembly (200, FIG. 2) is formed from two, interconnected circuit boards (202, 204). Conductive spacers (240) and a conductive material (260) are placed between complementary bond pads (218, 232) on the circuit boards. The conductive spacers are formed from a material that maintains its mechanical integrity during the process of attaching the circuit boards. The conductive material is a solder or conductive adhesive used to mechanically attach the circuit boards. In addition, an insulating material (270) is inserted into an interface region (250) between the circuit boards. The insulating material provides additional mechanical connection between the circuit boards. In one embodiment, one circuit board (202) includes a glass panel that holds an array of organic light emitting diodes (OLEDs), and the other circuit board (204) is a ceramic circuit board. Together, the interconnected circuit board assembly (200) forms a portion of a flat panel display (1102, FIG. 11).

Abstract: An metal programmable integrated circuit apparatus and method of manufacture and design using elevated metal layers for design-specific customization. The lower metal layer are used to form core cells and to provide power and clocking signals to the core cells. These core cell are customizable by the designer using only the upper metal layers. This new architecture allows faster turn-around time and fewer masks while keeping the time-to-market advantages of gate array structures.

Abstract: A semiconductor memory device of the present invention comprises, a semiconductor substrate, a drain region formed in the semiconductor substrate, a source region formed in the semiconductor substrate, a gate insulating film formed between the drain region and the source region on the semiconductor substrate, a floating gate electrode formed on the gate insulating film. The floating gate electrode has a projection portion on the end portion thereof.

Abstract: A thin film transistor includes a substrate having an upper side; a plurality of parallel-connected active layers supported on the upper side of the substrate; spaces defined between the substrate and the active layers; a first insulating layer on the plurality of active layers; a gate electrode on the first insulating layer over the plurality of active layers; and source and drain electrodes contacting the plurality of the active layers. The active layers of the thin film transistor are laser annealled to polycrystalline silicon. The spaces result in large polysilicon grains that result in good electrical characteristics.

Abstract: An integrated inductor is formed on an integrated circuit or other substrate. The inductor is formed of a stack of almost totally enclosed rings of conductive material in which each ring has a single gap. Vias connect adjacent rings on opposite sides of their gaps so as to form a coil shaped structure. The inductor has applications in filtering, in an oscillator, in an antenna, combined with an active detection circuit, combined with an electron source, in a microelectromechanial systems or MEMS, or the like. The inductor may be formed in a vertical orientation or in a horizontal orientation. Chemical mechanical polishing may be used for planarizing layers.

Abstract: A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

Abstract: A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

Abstract: Ferroelectric memory element having an MFIS structure including a silicon semiconductor substrate and an insulating film arranged above the silicon semiconductor substrate. The insulating film includes a low dielectric constant layer restraining film and a mutual diffusion preventive film so that an unnecessary, low dielectric constant layer is prevented from forming between the semiconductor substrate and the insulating film. A ferroelectric film is arranged on the insulating film. The low dielectric constant layer restraining film is thinner than the ferroelectric film.

Abstract: A technique for forming a high surface area electrode or storage node for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.

Abstract: A capacitive element structure in a semiconductor device having an interconnection structure. The capacitive element structure includes a capacitive element having a capacitive dielectric film made of an oxide compound. The capacitive element structure is above at least a bottom level interconnection of the interconnection structure.

Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

Abstract: A semiconductor device having high ESD resistance includes an internal circuit, an I/O pad, a division circuit connected to a lead-in line connecting the internal circuit and the I/O pad for outputting an electric signal from first and second terminals corresponding to an electric signal applied to the lead-in line and a clamp circuit including an MOS transistor for cutting off conduction when a difference in voltage between electric signals sent between the terminals is smaller in absolute value than a threshold voltage of the MOS transistor, and conducts when the absolute value is at least equal to the threshold voltage.

Abstract: The present invention relates to minimizing a leakage current in a floating island portion formed in a thin film transistor. More specifically, the present invention is directed to a thin film transistor including: a source electrode 14 and a drain electrode 15 disposed above an insulating substrate 11 at a predetermined interval; an s-Si film 16 disposed in relation to the source electrode 14 and drain electrode 15; a gate insulating film 17 overlapping the a-Si film 16; and a gate electrode 18 overlapping the gate insulating film 17, in which the a-Si film 16 is disposed between the source electrode 14 and the drain electrode 15 and has a floating island portion 20 above which or beneath which the gate electrode 18 is not formed, and boron ions are implanted into this portion to form a boron-ion-implanted region 19.

Abstract: A semiconductor device of the present invention has a plurality of capacitors having a cylindrical lower electrode which is formed along the side and the bottom surface of a recess formed in an insulator film over a semiconductor substrate and which is made of silicon having a lot of grained silicon on the surface, and a protector film with resistance to etching of a silicon oxide film is formed at least on the upper surface of the insulator film positioned between the adjacent lower electrodes.

Abstract: There is provided a semiconductor device including a storage capacitor having sufficient capacity and a minimum area. The storage capacitor of a pixel region has such a structure that a first storage capacitor and a second storage capacitor are stacked one on top of the other and are connected in parallel with each other. At that time, the first storage capacitor comprises a first capacitance electrode formed in the same layer as a drain region, a first dielectric, and a second capacitance electrode formed in the same layer as a gate wiring. The second storage capacitor comprises the second capacitance electrode, a second dielectric, and a third capacitance electrode formed in the same layer as a light-shielding film.

Abstract: Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt.

Abstract: The present invention has the object of obtaining a display device with a sufficient storage property without degrading the aperture ratio when high definition is to be achieved for the display device. In the active matrix display device, a good storage property can be obtained without degrading the aperture ratio by disposing the storage element below the pixel TFT area as shown in FIG. 3. Moreover, even when the area of the capacitor element is reduced, a sufficient amount of the capacitor can be obtained by laminating a plurality of capacitor elements.