Abstract: A charge trapping device, and a method of forming the same is disclosed. Charge traps are optimally distributed through a trapping region based on controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like. In some embodiments, FETs can be configured to include a negative differential resistance (NDR) characteristic when they utilize a particular charge trap energy and distribution.

Abstract: The present invention is to improve yield and reliability in a wiring step of a semiconductor device. When an Al wiring on an upper layer is connected through an connection pillar onto an Al wiring on a lower layer embedded in a groove formed on an interlayer insulation film, a growth suppression film having an opening whose width is wider than that of the Al wiring is formed on the interlayer insulation film and the Al wiring. In this condition, Al and the like are grown by a selective CVD method and the like. Accordingly, the connection pillar is formed on the Al wiring within the opening, in a self-matching manner with respect to the Al wiring.

Abstract: An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.

Abstract: A CVD Method of forming gate dielectric thin films on a substrate using metalloamide compounds of the formula M(NR1R2)x, wherein M is selected from the group consisting of: Zr, Hf, Y, La, Lanthanide series elements, Ta, Ti, Al; N is nitrogen; each of R1 and R2 is same or different and is independently selected from the group consisting of H, aryl, perfluoroaryl, C1–C8 alkyl, C1–C8 perfluoroalkyl, alkylsilyl and x is the oxidation state on metal M; and an aminosilane compound of the formula HxSi(NR1R2)4-x, wherein H is hydrogen; x is from 0 to 3; Si is silicon; N is nitrogen; each of R1 and R2 is same or different and is independently selected from the group consisting of H, aryl, perfluoroaryl, C1–C8 alkyl, and C1–C8 perfluoroalkyl. By comparison with the standard SiO2 gate dielectric materials, these gate dielectric materials provide low levels of carbon and halide impurity.

Abstract: An integrated circuit including a substrate, a conductive layer, at least one inductive element superposed on the conductive layer and formed by a metallic turn having an outer contour and an inner contour, which bound between them a surface referred to as the radiation surface, and insulating material for insulating the conductive layer from the inductive element. The conductive layer has a surface substantially identical to the radiation surface.

Abstract: The present invention is directed to organic photosensitive optoelectronic devices and methods of use for determining the position of a light source. Provided is an organic position sensitive detector (OPSD) comprising: a first electrode, which is resistive and may be either an anode or a cathode; a first contact in electrical contact with the first electrode; a second contact in electrical contact with the first electrode; a second electrode disposed near the first electrode; a donor semiconductive organic layer disposed between the first electrode and the second electrode; and an acceptor semiconductive organic layer disposed between the first electrode and the second electrode and adjacent to the donor semiconductive organic layer. A hetero-junction is located between the donor layer and the acceptor layer, and at least one of the donor layer and the acceptor layer is light absorbing.

Abstract: The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

Abstract: A bi-layer silicon electrode and its method of fabrication is described. The electrode of the present invention comprises a lower polysilicon film having a random grain microstructure, and an upper polysilicon film having a columnar grain microstructure.

Abstract: A light emitting element containing an organic compound has a disadvantage in that it tends to be deteriorated by various factors, so that the greatest problem thereof is to increase its reliability (make longer its life span). The present invention provides a method for manufacturing an active matrix type light emitting device and the configuration of such an active matrix type light emitting device having high reliability. In the method, a contact hole extending to a source region or a drain region is formed, and then an interlayer insulation film made of a photosensitive organic insulating material is formed on an interlayer insulation film. The interlayer insulation film has a curved surface on its upper end portion. Subsequently, an interlayer insulation film provided as a silicon nitride film having a film thickness of 20 to 50 nm is formed by a sputtering method using RF power supply.

Abstract: Support matrices for semiconductors are often encapsulated in a region of the bonding leads, the so-called bonding channel. The encapsulation is effected using a dispensable material that can flow onto the support matrix and causes contamination there. In order to prevent this flow, the support matrix for integrated semiconductors has a frame, conductor track structures and at least one bonding channel. In the bonding channel bonding leads or wires for connecting the conductor track structures to the integrated semiconductor are disposed. Disposed along the edge of the bonding channel a barrier for preventing the flow of flowable material from the bonding channel onto the frame and/or the conductor track structures. A method for producing such support matrices is likewise disclosed.

Abstract: A semiconductor device includes a base P region, a source N+ region, and a drain N+ region formed in a surface layer portion on a principal surface in an N? silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+ region in a region including the drain N+ region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+ region from the source N+ region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be attached to each conductive pad area such that the contact elements are arranged in a repeating pattern having a first pitch. The semiconductor device can also include translation traces, and each translation trace can be electrically connected to two or more of the conductive contact elements. Each translation trace can have a interconnect element attached thereto. The interconnect elements can be arranged in a repeating pattern having a second pitch substantially greater than the first pitch.

Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.

Abstract: The present invention relates to gate stack structure that is fabricated by a process for selectively plasma etching a structure upon a semiconductor substrate to form a designated topographical structure thereon utilizing an undoped silicon dioxide layer as an etch stop. In one embodiment, a substantially undoped silicon dioxide layer is formed upon a layer of semiconductor material. A doped silicon dioxide layer is then formed upon said undoped silicon dioxide layer. The doped silicon dioxide layer is etched to create the topographical structure. The etch has a material removal rate that is at least 10 times higher for doped silicon dioxide than for undoped silicon dioxide or the semiconductor material. One application of the inventive process includes selectively plasma etching a multilayer structure to form a self-aligned contact between adjacent gate stacks and a novel gate structure resulting therefrom.

Abstract: The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirements for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

Abstract: An integrated circuit, comprising: a predefined block of functional circuitry having a plurality of I/O pins; and a backside I/O pad electrically connected to each I/O pin through a backside via of the integrated circuit.

Abstract: A semiconductor storage device enables various plural memories to be mounted on the same package, and even though size of respective chips and/or position of bonding pad are different, it is capable of providing a stack MCP in which the chips are superimposed. It causes wiring sheet to intervene between an upper chip and a lower chip. There are provided bonding pads and a wiring pattern for connecting these bonding pads in the wiring sheet. A bonding pad of the upper chip is connected to the bonding pad by a first bonding wire, while the bonding pad is connected to a bonding pad of the package substrate by a second bonding wire. According to this construction, the signal from the upper chip is transmitted to the package substrate via the wiring sheet.

Abstract: An apparatus and method is described incorporating one or more layers of SiCOH and one or more layers of patterned conductors in an integrated circuit chip. The invention overcomes the problem of capacitance by lowering the k of the delectric and overcomes the problem of breakdown voltage and the leakage curent by tailoring the composition of SiCOH.