Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.

Abstract: A bipolar transistor includes a collector that is selected from the group SiC and SiC polytypes (4H, 6H, 15R, 3C . . . ), a base that is selected from the group Si, Ge and SiGe, at least a first emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, amorphous-SiC and diamond-like carbon, and at least a second emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, amorphous-SiC and diamond-like carbon. Direct-wafer-bonding is used to assemble the bipolar transistor. In an embodiment the bandgap of the collector, the bandgap of the at least a first emitter and the bandgap of the at least a second emitter are larger than the bandgap of the base.

Abstract: An organic field effect transistor (FET) is described with an active dielectric layer comprising a low-temperature cured dielectric film of a liquid-deposited silsesquioxane precursor. The dielectric film comprises a silsesquioxane having a dielectric constant of greater than 2. The silsesquioxane dielectric film is advantageously prepared by curing oligomers having alkyl(methyl) and/or alkyl(methyl) pendant groups. The invention also embraces a process for making an organic FET comprising providing a substrate suitable for an organic FET; applying a liquid-phase solution of silsesquioxane precursors over the surface of the substrate; and curing the solution to form a silsesquioxane active dielectric layer. The organic FET thus produced has a high-dielectric, silsesquioxane film with a dielectric constant of greater than about 2, and advantageously, the substrate comprises an indium-tin oxide coated plastic substrate.

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

Abstract: Manufacturable processes and the resultant structures utilize metal hydride as an internal source of hydrogen to enhance heat removal within semiconductor packages that employ low dielectric constant materials. The use of a metal hydride heated by internal or external sources facilitates pressurizing hydrogen gas or hydrogen-helium gas mixtures within a hermetically-sealed package. The configuration of the metal hydride can include, where needed to generate the pressure required in larger packages, a relatively large area of metal hydride material on at least one or a plurality of hydrogen generation-dedicated chips. Alternatively, the configuration can include at least one or a plurality of relatively small “islands” of metal hydride material on each of at least one or a plurality of integrated circuit-bearing chips.

Abstract: A semiconductor device has a capacitance insulating film having a perovskite structure represented by the general formula ABO3 (where each of A and B is a metal element) and first and second electrodes opposed to each other with the capacitance insulating film interposed therebetween. The capacitance insulating film is formed such that the composition of the metal element A or B is higher in the region thereof adjacent the first electrode than in the other region thereof.

Abstract: A board-shaped thermal conductor base board (3) is arranged on the bottom surface of a power module (1). Substrates (4) and (5) are arranged on the top surface of the thermal conductor base board (3), and semiconductor elements (6) and (7) are respectively arranged on the top surfaces of the substrates (4) and (5). The semiconductor elements (6, 7) are surrounded by a resinous case (2). A source electrode (13) is attached above and apart from the semiconductor elements (6, 7) by using the resinous case (2). The connection between the source electrode (13) and the sources of the semiconductor elements (7) are connected by wire bonding.

Abstract: According to one exemplary embodiment, a high-k dielectric stack situated between upper and lower electrodes of a MIM capacitor comprises a first high-k dielectric layer, where the first high-k dielectric layer has a first dielectric constant. The high-k dielectric stack further comprises an intermediate dielectric layer situated on the first high-k dielectric layer, where the intermediate dielectric layer has a second dielectric constant. According to this exemplary embodiment, the high-k dielectric stack further comprises a second high-k dielectric layer situated on the intermediate dielectric layer, where the second high-k dielectric layer has a third dielectric constant. The second dielectric constant can be lower than the first dielectric constant and the third dielectric constant.

Abstract: The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into the gate structure. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and filled into the undercut structure for storing carrier and source and drain regions formed adjacent to the gate structure and under the undercut structure. Salicide is formed on the gate structure and the source and drain regions.

Abstract: A semiconductor integrated circuit device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulating layer; source regions of a first conduction type and drain regions of the first conduction type both formed in the semiconductor layer; body regions of a second conduction type formed in the semiconductor layer between the source regions and the drain regions to store data by accumulating or releasing an electric charge; word lines formed on the body regions in electrical isolation from the body regions to extend in a first direction; bit lines connected to the drain regions and extending in a direction different from the first direction; and buried wirings formed in the insulating layer in electrical isolation from the semiconductor substrate and the semiconductor layer, said buried wirings extending in parallel with the bit lines.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.

Abstract: A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in only the high-voltage transistor prior to conducting an oxidation process to protect the substrate and gate electrode. After the oxidation process is performed, the low-voltage transistor is subjected to an LDD implantation process. The resultant semiconductor device provides a high-voltage transistor having a deeper LDD region junction depth than the low-voltage transistor, ensuring reliability and performance.

Abstract: A “Folded Cavity Surface Emitting Laser” (FCSEL) sum frequency generating device capable of generating a second harmonic at room temperatures with high efficiency and output power, while having a small size, low energy consumption, and a low manufacturing cost. A FCSEL sum frequency generating semiconductor diode laser has a multilayered structure that comprises a mode discriminating polyhedral shaped prism waveguide, which is located at one end of two light emitting diodes, a partial photon reflecting mirror, which is located at the opposite end of the two light emitting diodes, and a phase-matching sum-frequency generating superlattice, which is located between the polyhedral shaped prism waveguide and the partial photon reflecting mirror.

Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.

Abstract: A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped region is formed in the lightly doped region and lateral to the spacer. A lateral distance is kept between the spacer and the heavily doped region.

Abstract: A microwave monolithic integrated circuit (MMIC) package includes a MMIC and a base plate that is matched as to its coefficient of thermal expansion (CTE) with the MMIC. A solder preform is contained on the base plate. The MMIC is mounted on the solder preform. A chip cover covers the MMIC and are configured with respective portions that engage each other such that any pads on the MMIC are exposed for wire and ribbon bonding. The base plate and MMIC are secured together by a solder flow process from the solder preform.

Abstract: A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The higher doping density reduces the on-resistance of the transistor. Furthermore, the portion of the N-well generated beneath the source diffusion region produces a low-impedance path for the source region, which restricts the transistor current flow in between the drain region and the source region.

Abstract: A bipolar transistor includes a collector that is selected from the group SiC and SiC polytypes (4H, 6H, 15R, 3C . . . ), a base that is selected from the group Si, Ge and SiGe, at least a first emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, amorphous-SiC and diamond-like carbon, and at least a second emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, amorphous-SiC and diamond-like carbon. Direct-wafer-bonding is used to assemble the bipolar transistor. In an embodiment the bandgap of the collector, the bandgap of the at least a first emitter and the bandgap of the at least a second emitter are larger than the bandgap of the base.

Abstract: A laser oscillation apparatus includes a wavelength change unit for driving a wavelength selection element in a band-narrowing module and changing the oscillation wavelength of a laser beam to a target value, and an oscillation history memory for storing the oscillation state of the laser beam as an oscillation history. The wavelength change unit drives the wavelength selection element on the basis of the oscillation history and changes the oscillation wavelength of the laser beam to the target value.

Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.