Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.

Abstract: A method of making semiconductor device packages includes the steps of attaching a wafer to a dielectric layer, testing semiconductor devices in the wafer, and then dicing the layered assembly. The dielectric layer may be, for example, a flexible tape. The semiconductor devices may be chips containing integrated circuits or memory devices. The dicing operation may be performed by a circular saw or by another suitable apparatus. The chips may be connected to input/output devices, such as ball grid arrays, on the dielectric layer, before the testing and dicing steps. Full wafer testing may be-conducted through the ball grid arrays. A relatively stiff metal sheet may be included in the layered assembly before the testing and dicing steps. The metal material may be used as heat spreaders and/or as electrical ground planes. The chips may be connected to the ball grid arrays by wire bonds or flip chip bumps and vias through the dielectric layer.

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.

Abstract: There is disclosed a TAB style BGA type semiconductor device. This semiconductor device comprises a semiconductor chip on which an integrated circuit is formed, and a polyimide tape which has a conductive pattern and which is allowed to adhere to the semiconductor chip. The conductive pattern includes a bonding portion connected to the pad of the semiconductor chip, a pad portion connected to the outside electrode, and an electrically floating island-like portion in addition to a wiring portion for connecting the bonding portion and the pad portion.

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Abstract: There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat treatment time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides of one active layer and crystallization is made. A boundary portion where crystal growth from one catalytic element introduction region meets crystal growth from the other catalytic element introduction region is formed in a region which becomes a source region or drain region.

Abstract: The semiconductor device of the present invention includes: a substrate; a first conductor film supported by the substrate; an insulating film formed on the substrate to cover the first conductor film, an opening being formed in the insulating film; and a second conductor film, which is formed within the opening of the insulating film and is in electrical contact with the first conductor film. The second conductor film includes: a silicon-containing titanium nitride layer formed within the opening of the insulating film; and a metal layer formed over the silicon-containing titanium nitride layer. The metal layer is mainly composed of copper.

Abstract: An EEPROM cell device on a substrate is achieved. The device comprises, first, a selection transistor having gate, drain, source, and channel. The drain is defined as a cell bit line. An isolation transistor has gate, drain, source, and channel. The source is defined as a cell source line. Finally, a floating gate transistor has control gate, floating gate, drain, source, and channel. The drains and sources of each transistor comprise a diffusion layer in the substrate. The channels of each transistor comprise the substrate. The floating gate transistor drain is coupled to the selection transistor source. The floating gate transistor source is coupled to the isolation transistor drain. The device is programmed and erased by charge tunneling between the floating gate and the floating gate transistor channel. The device may further comprise an isolation well underlying the diffusion layer. A two transistor EEPROM cell is disclosed. Several array architectures using the EEPROM cell are disclosed.

Abstract: A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

Abstract: The present invention discloses a light-emitting diode and a method for manufacturing such a light-emitting diode with a direct band-gap III-V compound semiconductor material on a GaAs substrate. It is implemented by forming a first conductive electrode on the top edge of the epitaxial LED layer and a second conductive electrode opposite the first conductive electrode on the edge of a transparent substrate. Further, after the first conductive electrode and second conductive electrode are connected by chip bonding skill, it is selectively to remove the GaAs substrate and plate a transparent electrode on the top portion of the epitaxial LED layer. Therefore, when casting from P-N junction of the light-emitting diode, the light will go through with directions of the top portion of epitaxial layer and transparent substrate.

Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

Abstract: An active pixel sensor having a transparent conductor that directly contacts a conductive element in an interconnection structure to electrically connect the transparent conductor to a pixel sensor bias voltage is provided. The active pixel sensor includes a semiconductor substrate, the interconnection layer, which is formed over the substrate, and a pixel interconnection layer formed over the interconnection layer. Photo sensors that include a pixel electrode, an I-layer, and may include a P-layer are formed over the pixel interconnection layer. The transparent conductor is formed over the photo sensors and the conductive element exposed on the surface of the interconnection layer.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

Abstract: A unit pixel in a CMOS image sensor is employed to reduce a threshold voltage of a reset transistor by modifying a unit pixel circuit. The unit pixel in the CMOS image sensor including: a semiconductor substrate including an epitaxial layer in which an active area and a FOX area are defined; a photodiode formed in the epitaxial layer; a transfer transistor including source/drain regions disposed between the photodiode and a floating diffusion node, wherein a control signal is applied to a gate thereof; a reset transistor including source/drain regions disposed between the floating diffusion node and a VDD terminal, wherein a control signal is applied to a drain thereof; a drive transistor of which a gate is connected to the floating diffusion node and a drain is connected to the VDD terminal; and a selection transistor of which a drain is connected to the drain of the drive transistor and a source is connected to an output terminal, wherein a control signal is applied to a gate thereof.

Abstract: Disclosed is a method for forming a semiconductor assembly and the resulting assembly in which a flowable adhesive material which secures a die to a support and does not form an adhesive fillet. A flowable adhesive is deposited between the die and support so that it covers about 50 to about 90 percent of the bottom surface area of the die after the die is mounted to the support. The reduced surface coverage area prevents formation of an adhesive fillet.

Abstract: Disclosed is a liquid crystal display apparatus comprising a pair of substrates and a liquid crystal layer provided between the substrates, the liquid crystal layer containing a liquid crystal composition that exhibits a cholesteric phase. The liquid crystal composition contains a mixture of a chiral material and nematic liquid crystal. The liquid crystal display layer is configured to satisfies the following conditions: a viscosity a [cP] of the liquid crystal composition is in a range from 30 to 150; a dielectric anisotropy b of the liquid crystal composition is in a range from 5 to 50; a thickness c [?m] of the liquid crystal layer is in a range from 3 to 8; and a product of a, b, and c is not less than 3500.

Abstract: In order to substantially reduce temperature-dependent influences and attendant long switching times in the case of an optical liquid crystal modulator having at least one ferroelectric liquid crystal and in a method for operating an optical liquid crystal modulator, the ferroelectric liquid crystals are provided to have a DHF mode and to exhibit an operating range of an electric field of more than 20 V/?m at the location of the liquid crystal.

Abstract: According to one exemplary embodiment, a test structure for determining electromigration and interlayer dielectric failure comprises a first metal line situated in a metal layer of the test structure. The test structure further comprises a second metal line situated adjacent and substantially parallel to the first metal line, where the second metal line is separated from the first metal line by a first distance, and where the first distance is substantially equal to minimum design rule separation distance. The test structure further comprises an interlayer dielectric layer situated between the first metal line and the second metal line. According to this exemplary embodiment, electromigration failure is determined when a first resistance of the first metal line or a second resistance of the second metal line is greater than a predetermined resistance, and interlayer dielectric failure is determined when a first current is detected between the first and second metal lines.

Abstract: A technique for reducing current crowding on a bump using selective current injection is provided. The technique allows a bump to more uniformly inject current around the bump from vias on a metal layer, where the vias are concentrated on outer regions of the metal layer and have higher via density than that of a central region of vias on the metal layer. Because vias are concentrated on the outer regions of the metal layer, higher current distribution density along current flow paths from the outer regions to the bump compensates for a shorter current path length from the central region to the bump, thus effectively reducing current crowding on the bump. Further, a technique for selectively positioning regions of vias on a metal layer in order to reduce current crowding on a bump is provided.