Abstract: An electrical device includes electrical contact pads, a supply voltage bus and an interconnection circuit. The electrical contact pads receive a supply voltage, and the bus is electrically connected to the electrical contact pads. For each electrical contact pad, the interconnection circuit forms a redundant connection between the bus and the electrical contact pad. The electrical device may include a passivation layer that includes windows to establish electrical contact between the electrical contact pads and the supply voltage bus. This window may be elongated in a path that is generally aligned with the path along which the supply voltage bus extends.

Abstract: A method of early and effective detection of plasma damage to a gate oxide layer by a special design of the active region is achieved. A plasma-damage testing structure is fabricated by providing a gate electrode overlying an active area of a semiconductor substrate wherein a gate oxide layer underlies the gate electrode. A portion of the active area underlying the gate electrode has sharp corners. The plasma-damage testing structure is exposed to a plasma environment. Electrical tests are performed to detect plasma damage to the plasma-damage testing structure. This model provides an accurate evaluation of plasma damage to actual MOSFET's.

Abstract: Disclosed is a triple metal line 1T/1C ferroelectric memory device and a method to make the same. A ferroelectric capacitor is connected to the transistor through a buried contact plug. An oxidation barrier layer lies between the contact plug and the lower electrode of the capacitor. A diffusion barrier layer covers the ferroelectric capacitor to prevent diffusion of material into or out of capacitor. As a result of forming the oxidation barrier layer, the contact plug is not exposed to the ambient oxygen atmosphere thereby providing a reliable ohmic contact between the contact plug and the lower electrode. Also, the memory device provides a triple interconnection structure made of metal, which improves device operation characteristics.

Abstract: An upper reflecting layer in a main region, a first support region and a second support region is separated from an upper reflecting layer in the surrounding region by separating grooves. The first support region and the second support region are folded in a valley shape from a substrate at grooves, and the first support region, the second support region and the main region are folded in a mountain shape, and the upper reflecting layer in the main region faces parallel to the substrate with spacing.

Abstract: A metal-to-metal capacitor in a semiconductor integrated circuit is converted to a conductive structure by connecting the first metal plate of the capacitor to ground and the second metal plate of the capacitor to a programming voltage, thus causing the insulator material to breakdown and conduct current from the first plate to the second plate.

Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: A semiconductor device, having a high breakdown voltage transistor and a low breakdown voltage transistor in a common substrate with different driving voltages, includes a semiconductor substrate of a first conductivity type, a first triple well formed in the semiconductor substrate and having a first well of a second conductivity type and a second well of the first conductivity type formed within the first well, a second triple well formed in the semiconductor substrate and having a third well of the second conductivity type and a fourth well of the first conductivity type formed within the third well, a low breakdown voltage transistor of the second conductivity type formed at the second well, and a high breakdown voltage transistor of the second conductivity type formed at the fourth well. The first well of the first triple well can have an impurity concentration higher than an impurity concentration of the third well of the second triple well.

Abstract: A semiconductor photodetection device includes a semiconductor structure including an optical absorption layer having a photo-incidence surface on a first side thereof, a dielectric reflecting layer formed on a second side of the semiconductor structure opposite to the first side, a contact electrode surrounding the dielectric reflecting layer and contacting with the semiconductor structure, and a close contact electrode covering the dielectric reflecting layer and contacting with the contact electrode and the dielectric reflecting layer, wherein the close contact electrode adheres to the dielectric reflecting layer more strongly than to the contact electrode.

Abstract: A packaging structure suitable for an integrated circuit device receiving short-wavelength laser light is provided. The integrated circuit device having a photo detecting part, leads and wires for connection therebetween are encapsulated in an encapsulation section. A recess is formed on the light incident surface of the encapsulation section above the photo detecting part, to thin the encapsulation section on the surface of the photo detecting part and thereby reduce the energy of light absorbed by the encapsulation section.

Abstract: A thin film transistor and a pixel structure with the same are disclosed. The thin film transistor includes a gate electrode with at least one notch, a gate dielectric layer, a source region, a drain region, and a channel layer. The gate electrode is on a substrate. The gate dielectric layer is on the substrate and covers the gate electrode. The source region is on the gate dielectric layer, wherein it is over a region outside the notch of the gate electrode and overlaps a portion of the gate electrode. The drain region is on the gate dielectric layer, wherein it is over the notch of the gate electrode and overlaps the gate electrode at the edge of the notch. Further, the channel layer is on the gate dielectric layer and between the source and drain regions. Due to asymmetric design of the source and drain regions, the parasitic capacitance change can be substantially reduced when a misalignment of the upper and lower metal layers occurs.

Abstract: A noise-proof, integrated semiconductor current detector is disclosed which has formed in a semiconductor substrate a Hall generator for providing a Hall voltage in proportion to the strength of a magnetic field applied, a control current supply circuit for delivering a control current to the Hall generator, and a Hall voltage output circuit for putting out the Hall voltage for detection or measurement. The Hall generator, control current supply circuit, and Hall voltage output circuit are all exposed at one of the pair of opposite major surfaces of the semiconductor substrate. A current-path conductor is attached to this one major surface of the substrate via insulating layers for carrying a current to be detected.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

Abstract: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor and/or the transistor are provided. The bismuth titanium silicon oxide has good dielectric properties and is thermally and chemically stable. The bismuth-titanium-silicon oxide thin film can be effectively used as a dielectric film of a capacitor or as a gate dielectric film of a transistor in a semiconductor device. Various electronic devices having good electrical properties can be manufactured using the capacitor and/or the transistor having the bismuth-titanium-silicon oxide film.

Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract: In a CMOS circuit formed on a substrate 101, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 107a are provided in an n-channel TFT. The LDD regions 113 overlaps the first wiring line 102a and does not overlap the second wiring line 107a. Thus, when a gate voltage is applied to the first wiring line, the GOLD structure is formed, while no applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.

Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.

Abstract: A light emitting diode comprising a light emitting diode element 20 mounted on a glass epoxy substrate 12, this light emitting diode element 20 being protected at its surface side by a resin seal member 33, in which: a light emitting diode element for blue luminescence, formed of gallium nitride type compound semiconductor is used as the above-mentioned light emitting diode element 20; and a fluorescent material containing layer 21 composed of a fluorescent material containing layer 21 composed of a fluorescent material dispersed into an adhesive is arranged on the back side of this light emitting diode element. On the back side of the light emitting diode element 20, blue luminescence is converted in wavelength to produce white luminescence of high intensity.

Abstract: A thyristor-based semiconductor device has a control port formed in a trench having a height-to-width aspect ratio that can be prohibitive to filling a bottom portion of the trench with an insulative material. According to an example embodiment of the present invention, a trench is formed in the substrate adjacent to a thyristor region, and a control port is formed near a bottom of the trench. An upper portion of the trench is then filled, thereby covering the control port. The control port is adapted to reduce the aspect ratio of a remaining portion of the trench over the control port, making it possible to fill trenches having a high height-to-width aspect ratio (e.g., at least 2:1). The thyristor control port is capacitively coupled to the thyristor region via a dielectric on a sidewall of the trench, and is configured and arranged to control current in the thyristor body via the capacitive coupling.