Abstract: A semiconductor device to be mounted on an external electronic device includes a film substrate on which wiring electrodes are formed, the wiring electrodes being partially covered with a covering member; and a semiconductor chip mounted on the film substrate. In this semiconductor device, the film substrate is folded so that at least one edge of the film substrate is on a side opposite to a side on which the semiconductor chip is mounted, and portions of the wiring electrodes exposed from the covering member on a surface of the film substrate on which the semiconductor chip is mounted are to be connected to electrodes of an external electronic device.

Abstract: A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source.

Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.

Abstract: A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends vertically along a sidewall of the trench and a second portion that extends horizontally along the substrate surface. An electrically conductive floating gate is formed over and insulated from a portion of the channel region. A raised source line of conductive material is disposed over the source region, and laterally adjacent to and insulated from the floating gate. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.

Abstract: A method is proposed for fabricating a TFBGA (Thin & Fine Ball-Grid Array) package with embedded heat spreader. Conventionally, since an individual TFBGA package is quite small in size, it would be highly difficult to incorporate an embedded heat spreader therein. As a solution to this problem, the proposed method utilizes a single substrate predefined with a plurality of package sites, and further utilizes a heat-spreader frame including an integrally-formed matrix of heat spreaders each corresponding to one of the package sites on the substrate. A batch of semiconductor chips are then mounted on the respective package sites on the substrate. During the encapsulation process, a single continuous encapsulation body is formed to encapsulate the entire heat-spreader frame and all the semiconductor chips. After ball implantation, a singulation process is performed to cut apart the encapsulation body into individual package units, each serving as the intended TFBGA package.

Abstract: A memory cell transistor of a DRAM device is provided. A gate stack pattern is formed on a semiconductor substrate. A DC node and a BC node are formed substantially under lateral sides of the gate stack pattern in the semiconductor substrate. The DC node and the BC node are being electrically connected to a bit line and a storage electrode of a capacitor respectively. A first source/drain junction region is formed under the DC node and a second source/drain junction region is formed under the BC node. The first source/drain junction region has a profile which is different from that of the second source/drain junction region.

Abstract: A vertical routing structure inside a substrate for connecting a pair of trace lines electrically. The trace lines are positioned on the top and bottom surface of a stack layer. The vertical routing structure includes a conductive rod and two bonding pads. The conductive rod passes through the stack layer such that the top and bottom surface of the conductive rod are also exposed on the top and bottom surface of the stack layer. In addition, a bonding pad is also attached to the top and bottom surface of the conductive rod respectively. The bonding pads are connected to the aforementioned trace lines. The two bonding pads have a transverse sectional area smaller than the transverse sectional area of the conductive rod. Thus, the vertical routing structure is able to reduce surface area needed to accommodate inter-layer connections and increase routing density within the substrate.

Abstract: A semiconductor device is provided which includes a first semiconductor chip, a substrate onto which the first semiconductor chip is flip-chip bonded and on which a concave is formed along one side of the first semiconductor chip which is flip-chip bonded, a second semiconductor chip which is flip-chip bonded onto a portion on the substrate opposite the first semiconductor chip across the concave on the substrate, and a resin applied to spaces between the substrate and the first and second semiconductor chips.

Abstract: A method of forming a semiconductor structure comprises forming an etch-stop layer comprising nitride, on a stack. The stack is on a semiconductor substrate, and the stack comprises (i) a gate layer. The forming is by CVD with a gas comprising a first compound which is SixL2x, and a second compound comprising nitrogen and deuterium, L is an amino group, and X is 1 or 2.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer.

Abstract: A liquid crystal display device, and a fabricating method thereof, having organic pixel electrodes. The organic pixel electrodes are benefically comprised of a light sensitive organic material, preferably PEDOT (polyethylenedioxythiophene). The organic pixel electrodes are rendered electrically conductive using light. The method of fabricating a liquid crystal display device coating or screen printing a TFT substrate with the light sensitive organic material, and then illuminating selected portions of the light sensitive material to form the organic pixel electrodes.

Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.

Abstract: A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p-type doping regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n? drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n? drift layer; a pair of field oxide regions and termination region formed into the n? drift layer and each spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer.

Abstract: A non-volatile memory cell and a high voltage MOS transistor on the same semiconductor chip without changing the characteristic of the non-volatile memory cell. A gate insulating film of a MOS transistor is formed using the steps of forming an oxide film 12 formed on a floating gate 14 of a split-gate type non-volatile memory cell and of forming a tunneling insulating film 16 formed on the floating gate 14 and the oxide film 12. The gate insulating film 13 of the MOS transistor is formed by a stacked layer of the oxide film 12 and tunneling insulating film 16. Thus, the quantity of heat treatment in the entire production process undergoes no change, and the optimized characteristic of the non-volatile memory undergoes no change.

Abstract: A method and apparatus for employing a light shield to modulate pixel color responsivity. The improved pixel includes a substrate having a photodiode with a light receiving area. A color filter array material of a first color is disposed above the substrate. The pixel has a first relative responsivity. A light shield is disposed above the substrate to modulate the pixel color responsivity. The light shield forms an aperture whose area is substantially equal to the light receiving area adjusted by a reduction factor. The reduction factor is the result of an arithmetic operation between the first relative responsivity and a second relative responsivity, associated with a second pixel of a second color.

Abstract: A method is proposed for fabricating a TFBGA (Thin & Fine Ball-Grid Array) package with embedded heat spreader. Conventionally, since an individual TFBGA package is quite small in size, it would be highly difficult to incorporate an embedded heat spreader therein. As a solution to this problem, the proposed method utilizes a single substrate predefined with a plurality of package sites, and further utilizes a heat-spreader frame including an integrally-formed matrix of heat spreaders each corresponding to one of the package sites on the substrate. A batch of semiconductor chips are then mounted on the respective package sites on the substrate. During the encapsulation process, a single continuous encapsulation body is formed to encapsulate the entire heat-spreader frame and all the semi-conductor chips. After ball implantation, a singulation process is performed to cut apart the encapsulation body into individual package units, each serving as the intended TFBGA package.