Patents Examined by George R. Fourson
  • Fabrication of thin film germanium infrared sensor by bonding to silicon wafer
    Patent number: 7157300
    Abstract: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: January 2, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Jer-Shen Maa, Sheng Teng Hsu, Douglas J. Tweet
  • Methods of forming openings, and methods of forming container capacitors
    Patent number: 7153778
    Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Luan C. Tran, Ardavan Niroomand, Fred D. Fishburn, Yoshiki Hishiro, Ulrich C. Boettiger, Richard D. Holscher
  • Etching method, method of manufacturing semiconductor device, and semiconductor device
    Patent number: 7153710
    Abstract: In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-step manner, whereby enabling the control of the etching amount at high precision.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: December 26, 2006
    Assignee: Sony Corporation
    Inventor: Tomoya Nishida
  • Strained Si/SiGe/SOI islands and processes of making same
    Patent number: 7153753
    Abstract: A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use of a minifield oxidation process. The recess is filled to form a shallow trench isolation structure. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Self-aligned, silicided, trench-based, DRAM/EDRAM processes with improved retention
    Patent number: 7153737
    Abstract: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.
    Type: Grant
    Filed: January 17, 2005
    Date of Patent: December 26, 2006
    Assignee: International Business Machines Corporation
    Inventors: Oh-Jung Kwon, Kim Bosang, Herbert Lei Ho, Babar Ali Khan, Deok-kee Kim
  • Long retention time single transistor vertical memory gain cell
    Patent number: 7151024
    Abstract: A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lower thermally dependent leakage currents which enables significantly longer refresh intervals. In certain applications, the cell is effectively non-volatile provided appropriate gate bias is maintained. N-type source and drain regions are provided along with a pillar vertically extending from a substrate, which are both p-type doped. A floating body region is defined in the pillar which serves as the body of an access transistor as well as a body storage capacitor. The cell provides high volumetric efficiency with corresponding high cell density as well as relatively fast read times.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: December 19, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability
    Patent number: 7151028
    Abstract: According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: December 19, 2006
    Assignee: Spansion LLC
    Inventors: Shenqing Fang, Rinji Sugino, Kuo-Tung Chang, Zhigang Wang, Kazuhiro Mizutani, Pavel Fastenko
  • Semiconductor on insulator device architecture and method of construction
    Patent number: 7148121
    Abstract: An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14 is used to provide a cohesive bond with a buried insulator layer 18. The semiconductor device layer 20 is formed on the outer surface of buried insulator layer 18. An inductive well 22 can be formed to provide a platform for the formation of inductive devices 34 within an inductive region 26.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: December 12, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Magnetoresistive random access memory device structures and methods for fabricating the same
    Patent number: 7144744
    Abstract: Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: December 5, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mitchell T. Lien, Mark A. Durlam, Thomas V. Meixner, Loren J. Wise
  • Semiconductor device with Schottky electrode including lanthanum and boron, and manufacturing method thereof
    Patent number: 7144765
    Abstract: A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: December 5, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiharu Anda, Akiyoshi Tamura
  • Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures
    Patent number: 7141486
    Abstract: A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying the first trench. Silicon dioxide fills both the first and the second trenches to form the shallow trench isolation structure, with the silicon dioxide in the first trench exhibiting a negative taper angle to avoid formation of polysilicon stringers during a gate polysilicon deposition.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: November 28, 2006
    Assignee: Agere Systems Inc.
    Inventors: Nace Rossi, Ranbir Singh, Arun K. Nanda
  • Semiconductor wafer dividing method utilizing laser beam
    Patent number: 7141443
    Abstract: A method which can divide a semiconductor wafer sufficiently precisely along a street by use of a laser beam, while fully avoiding or suppressing contamination of circuits formed in rectangular regions on the face of the semiconductor water, and without causing chipping to the rectangular regions on the face. A laser beam is applied from beside one of the back and the face of a semiconductor substrate and focused onto the other of the back and the face of the semiconductor substrate, or the vicinity thereof, to partially deteriorate at least a zone ranging from the other of the back and the face of the semiconductor substrate to a predetermined depth.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: November 28, 2006
    Assignee: Disco Corporation
    Inventors: Yusuke Nagai, Satoshi Kobayashi
  • Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits
    Patent number: 7141485
    Abstract: A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized and etched back. Next a barrier cap layer is deposited that is different than the underlying low k dielectric layer. In one embodiment, the barrier cap layer is a SiCOH material that is modified for enhanced CMP performance that yields fewer surface scratches and defects. A nitride etch stop layer and a pad oxide are removed above an active area on the substrate to afford the final STI structure. Optionally, the barrier cap layer is omitted and the low k dielectric layer extends slightly above the substrate level. Total parasitic capacitance in the resulting MOS device is reduced by 15% or more.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: November 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ke-Wei Su, Cheng Hsiao, Jaw-Kang Her
  • Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device
    Patent number: 7132710
    Abstract: A semiconductor device with a stack type capacitor having a lower electrode formed of an aluminum-doped metal, and a manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate having a gate structure and an active region; an interlayer dielectric film formed on the active region; a lower electrode formed of a metal containing aluminum on the interlayer dielectric film; a dielectric layer formed on the lower electrode; an upper electrode formed on the dielectric layer; and a plug formed in the interlayer dielectric film to electrically connect the active region with the lower electrode.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: November 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hion-suck Baik, Jung-hyun Lee, Jong-bong Park, Yun-chang Park
  • Method for forming ferroelectric film and semiconductor device
    Patent number: 7132300
    Abstract: In a method for forming a ferroelectric film of insulating metal oxide on a surface of an electrode with a concave or a convex or in convex shape which is formed above a substrate, multiple types of source gases constituting a material gas and each containing an organometallic compound are introduced into a chamber and main components of the multiple types of source gases are allowed to chemically react with one another with the chemical reaction proceeding depending on the reaction rate. Then, the ferroelectric film is deposited on the surface of the electrode.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: November 7, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshitaka Tatsunari, Shinichiro Hayashi
  • Method of reducing fringing capacitance in a MOSFET
    Patent number: 7132342
    Abstract: In a method of reducing the fringing capacitance of a MOSFET, the nitride spacers on the sides of the MOSFET gate are etched away to form trenches, which are plugged to define air spacers.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: November 7, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Alexei Sadovnikov, Peter Johnson
  • Memory cell intermediate structure
    Patent number: 7126179
    Abstract: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material may be deposited on the surface and within the via. A hard mask of a flowable oxide is deposited over the metallic material in the via to protect the metallic material in the via, A subsequent dry sputter etch removes the metallic meterial from the surface of the insulator and a portion of the hard mask. After complete removal of the hard mask, a glass material is recessed over the metallic material in the via. Then, a layer of a metal-containing material is formed over the glass material. Finally, a second conductor is formed on the surface of the insulator.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: October 24, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Jiutao Li
  • Oxidation method for semiconductor process
    Patent number: 7125811
    Abstract: An oxidation method for a semiconductor process, which oxidizes a surface of a target substrate, includes heating a process container that accommodates the target substrate, and supplying hydrogen gas and oxygen gas into the process container while exhausting the process container. The oxidation method also includes causing the hydrogen gas and the oxygen gas to react with each other in the process container at a process temperature and a process pressure to generate water vapor, and oxidizing the surface of the target substrate by the water vapor. The process pressure is set at 2000 Pa (15 Torr) or more.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: October 24, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kazuhide Hasebe
  • Methods for making microwave circuits including a ground plane
    Patent number: 7125752
    Abstract: In a method for making a microwave circuit, a first dielectric is deposited over a ground plane, and then a conductor is formed on the first dielectric. A second dielectric is then deposited over the conductor and first dielectric, thereby encapsulating the conductor between the first and second dielectrics. In one embodiment, a ground shield layer is formed over the first and second dielectrics by 1) precoating the first and second dielectrics with a metallo-organic layer, and then 2) depositing a thickfilm ground shield layer over the precoat layer. Alternately, a ground shield layer is formed over the first and second dielectrics by 1) placing a polymer screen over the first and second dielectrics, and applying pressure to the polymer screen until it at least partially conforms to a contour of the dielectrics, and then 2) printing a thickfilm ground shield layer through the polymer screen.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 24, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: John F. Casey, Lewis R. Dove, Ling Liu, James R. Drehle, R. Frederick Rau, Jr., Rosemary O. Johnson, Julius Botka
  • Deep trench capacitor with buried plate electrode and isolation collar
    Patent number: 7122437
    Abstract: A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: October 17, 2006
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Thomas W. Dyer, Chun-yung Sung, Ravikumar Ramachandran, Ramachandra Divakaruni, Carl Radens