Patents Examined by Getente A Yimer
  • Patent number: 11782604
    Abstract: A method, computer program product, and computing system for executing a plurality of IO traces on a storage system. At least one vertical flow and at least one horizontal flow associated with the at least one vertical flow may be defined for the plurality of IO traces. A hierarchical representation of the plurality of IO traces may be generated with the at least one vertical flow and the at least one horizontal flow associated with the at least one vertical flow defined for the plurality of IO traces.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: October 10, 2023
    Assignee: EMC IP Holding Company, LLC
    Inventors: Geng Han, Vladimir Shveidel, Jibing Dong
  • Patent number: 11762792
    Abstract: A marine-type communication device that reads data from a data bus, dynamically creates new data channels for a plurality of operational systems and performs a volatility assessment to determine when to save the data for transmission to a cloud network and when to transmit the data to the cloud network.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: September 19, 2023
    Assignee: Siren Marine, Inc.
    Inventors: Daniel A. Harper, Dave Morschhauser, Phillip King Gaynor
  • Patent number: 11762791
    Abstract: A system and a method for detecting baseboard management controller (BMC) includes the BMC and a CPLD. The BMC includes a GPIO and configured to drive the GPIO to output a first signal. The CPLD is connected to the GPIO and is configured to determine a status of the BMC by detecting whether the GPIO outputs the first signal. When the CPLD detects that the GPIO is not outputting the first signal, the CPLD determines that the BMC is in an abnormal status; when the CPLD detects that the GPIO is outputting the first signal and a level status of the first signal is switched in a predetermined time, the CPLD determines that the BMC is in a normal status.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: September 19, 2023
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventor: Li-Yun Hao
  • Patent number: 11755238
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to deliver a continuous DQS signal, determine whether a fill rate of a write buffer or an emptying rate of read buffer is sufficient to continuously send user data to the memory device or from the memory device, evaluate timing for sending or receiving the user data, and transfer data to or from the memory device continuously with the DQS signal. The data sent to the memory device includes the user data and garbage data, where the user data and the garbage data are separately transferred. The data received from the memory device includes user data that is sampled and user data that is not sampled, where the user data that is sampled and the user data that is not sampled are separately received.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: September 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11748290
    Abstract: A multi-host system, a host equipment, and an operation method for sharing a human-machine interface device are provided. The host equipment is controlled by human interface device (HID) operation information from another host equipment. The host equipment includes a universal serial bus (USB) host and a USB bridge device. The USB host receives the HID operation information from the another host equipment through a communication channel, and outputs the HID operation information through a USB downstream port of the USB host. A USB upstream port of the USB bridge device is coupled to the USB downstream port of the USB host to receive the HID operation information. The USB bridge device returns the HID operation information in an HID report form to the USB downstream port of the USB host through the USB upstream port of the USB bridge device.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: September 5, 2023
    Assignee: GENESYS LOGIC, INC.
    Inventor: Wei-Te Lee
  • Patent number: 11741029
    Abstract: A system and method for input/output communication is disclosed. In one embodiment, a device identifies a queue including a plurality of input/output (I/O) descriptors, each of the plurality of I/O descriptors representing one of: an active descriptor associated with an active I/O request or an executed descriptor that is associated with an executed I/O request. The device retrieves, from a first index in the queue, one or more active descriptors associated with an I/O request. The device executes the I/O request. The device writes a first executed descriptor to a second index in the queue, where the first executed descriptor indicates the I/O request has been executed.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: August 29, 2023
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11741350
    Abstract: A computer-implemented method includes receiving a neural network model for implementation using a processing element array, where the neural network model includes a convolution operation on a set of input feature maps and a set of filters. The method also includes determining, based on the neural network model, that the convolution operation utilizes less than a threshold number of rows in the processing element array for applying a set of filter elements to the set of input feature maps, where the set of filter elements includes one filter element in each filter of the set of filters. The method further includes generating, for the convolution operation and based on the neural network model, a first instruction and a second instruction for execution by respective rows in the processing element array, where the first instruction and the second instruction use different filter elements of a filter in the set of filters.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 29, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeffrey T. Huynh, Ron Diamant, Hongbin Zheng, Yizhi Liu, Animesh Jain, Yida Wang, Vinod Sharma, Richard John Heaton, Randy Renfu Huang, Sundeep Amirineni, Drazen Borkovic
  • Patent number: 11741023
    Abstract: A method of a pointing device which is used to be coupled to a host system through a universal serial bus (USB) communication interface includes: providing a USB driver device to communicate with the host system via the USB communication interface; monitoring a specific voltage change or a specific data transmission state of the USB communication interface to generate a monitoring result; and correcting a USB state of the USB driver device when the monitoring result indicates that a undefined or abnormal behavior of the host system occurs.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: August 29, 2023
    Assignee: PixArt Imaging Inc.
    Inventors: Ching-Chih Chen, Jr-Yi Li
  • Patent number: 11741339
    Abstract: A method and an apparatus for quantizing an activation volume of a deep neural network are disclosed. The method includes: obtaining an activation volume of a network layer in the deep neural network (S101), wherein elements in the activation volume are arranged in three directions: height, width, and depth; dividing depth segments in the activation volume in which a difference among element features is smaller than a preset threshold into a same slice group along the depth direction of the activation volume, so as to obtain a plurality of slice groups (S102); quantizing each slice group respectively by using a quantization parameter corresponding to each slice group obtained through a quantization formula (S103). The quantization error can be reduced through the above method.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 29, 2023
    Assignee: Hangzhou Hikvision Digital Technology Co., Ltd.
    Inventor: Yuan Zhang
  • Patent number: 11733872
    Abstract: A system includes a transmission device and a reception device that are connected through a link. The reception device includes a reception buffer configured to receive and store transaction layer packets and a reception flow controller configured to generate flow control packets by monitoring an occupation state of the reception buffer. The transmission device includes a transmission buffer, a transmission flow controller and a dynamic frequency controller. The transmission buffer stores pending transaction layer packets to be transferred to the reception device. The transmission flow controller controls a flow of transaction layer packets to be transferred to the reception device based on the flow control packets received from the reception device. The dynamic frequency controller controls a frequency of an internal clock signal of the transmission device by monitoring a state of the transmission buffer and a state of the transmission flow controller.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: August 22, 2023
    Inventors: Jaehwan Lim, Walter Jun, Jaeeun Kim, Jihoon Kim, Kihyeon Myung, Hyunjung Yoo, Jungwoo Lee
  • Patent number: 11726934
    Abstract: A method for registering a handler in a configured sequence of handlers includes: receiving, by a processor and memory implementing a sequencer infrastructure, a configuration script defining a sequence including one or more handler identifiers and corresponding one or more handler arguments; invoking a handler initialization entry point for a handler corresponding to a handler identifier, the invoking the handler initialization entry point including: selecting, based on the corresponding one or more handler arguments, a handler type from among two or more of: a configured instance of the handler; a configured alternate handler different from the handler; an alternate sequence of handlers; an expression; and a no-op handler; and initializing a configured handler based on the handler type selected and the corresponding one or more handler arguments; and adding the configured handler to a configured sequence of handlers.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: August 15, 2023
    Assignee: Level 3 Communications, LLC
    Inventor: William Crowder
  • Patent number: 11726931
    Abstract: The present disclosure describes apparatuses and methods for artificial intelligence-enabled management of storage media. In some aspects, a media access manager of a storage media system receives, from a host system, host input/output commands (I/Os) for access to storage media of the storage media system. The media access manager provides information describing the host I/Os to an artificial intelligence engine and receives, from the artificial intelligence engine, a prediction of host system behavior with respect to subsequent access of the storage media. The media access manager then schedules, based on the prediction of host system behavior, the host I/Os for access to the storage media of the storage system. By so doing, the host I/Os may be scheduled to optimize host system access of the storage media, such as to avoid conflict with internal I/Os of the storage system or preempt various thresholds based on upcoming idle time.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: August 15, 2023
    Assignee: Marvell Asia PTE, Ltd.
    Inventors: Christophe Therene, Nedeljko Varnica, Phong Sy Nguyen
  • Patent number: 11726660
    Abstract: Techniques providing connectivity between a CPU and physical storage devices (PDs) can use a loop back path formed between two connectors of an extended PO slot when an extended I/O card is inserted therein. The two connectors can include a first connector having connectivity with the CPU over a first set of lanes, and a second connector having connectivity with the PDs over a second set of lanes. While the extended I/O card is inserted into the I/O slot, connectivity can be provided between the CPU and the PDs using connectivity provided between the CPU and the first connector and the first set of lanes; using the loop back path provided between the first and second connectors; and using connectivity provided between the second connector and the PDs over the second set of lanes.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: August 15, 2023
    Assignee: Dell Products L.P.
    Inventors: Aric Hadav, Thomas N. Dibb, Amitai Alkalay
  • Patent number: 11720788
    Abstract: A calculation scheme decision system includes a pre-calculation unit performing, in an execution environment in which calculation is performed, calculation for each of respective layers of the network structure using at least one of calculation schemes prepared in advance for the respective layers, a cost acquisition unit acquiring a calculation cost of at least one calculation scheme for each layer based on a result of the calculation by the pre-calculation unit, a decision unit selecting one calculation scheme for each layer based on the calculation cost from among at least one of the calculation schemes prepared in advance for the respective layers to associate the layer with the selected one calculation scheme, and a calculation unit performing the calculation for each of the respective layers of the network structure on input data in the execution environment using the calculation scheme associated with each layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 8, 2023
    Assignee: Morpho Inc.
    Inventors: Masaki Hiraga, Yasuhiro Kuroda, Hitoshi Matsuo, Hideaki Nishino, Kouta Kurihara
  • Patent number: 11714763
    Abstract: Examples described herein relate to a network interface controller apparatus, that includes a processor component comprising at least one processor to generate remote memory access communications to access a first group of one or more namespaces; storage interface circuitry to generate remote memory access communications to access a second group of one or more namespaces; and a storage configuration circuitry with a device interface that is accessible through a user space driver, the storage configuration circuitry to set the first and second group of one or more namespaces. In some examples, the device interface is compatible with Peripheral Component Interconnect Express (PCIe) and the storage configuration circuitry is accessible as a physical function (PF) or a virtual function (VF).
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 1, 2023
    Assignee: Intel Corporation
    Inventors: Yadong Li, Jose Niell, Kiel Boyle
  • Patent number: 11714767
    Abstract: A system and method for performing a combined storage operation, the method including using a direct memory access (DMA) controller to obtain a modified DMA command, wherein the modified DMA command includes parameters of a data manipulation and one of a user read command or a user write command; retrieve data according to the user read command or the user write command; manipulate the data according to the parameters of a data manipulation, inline with the user read command or the user write command; and transmit the manipulated data according to the user read command or the user write command.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 1, 2023
    Assignee: LIGHTBITS LABS LTD.
    Inventors: Roii Goldstein, Ofer Hayut, Roy Geron
  • Patent number: 11704262
    Abstract: A reconfigurable hardware platform uses, in place of a portion of software, a chain of reconfigurable hardware Operator Blocks to manipulate data as the data moves down the chain. This conveyor belt architecture, or chain of Operator Blocks, moves data from Operator Block to Operator Block. This conveyor belt architecture processor may be combined with a conventional front-end processor to process complex information or critical loops in hardware while processing a rest of a program as software.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: July 18, 2023
    Inventors: Zia Shlaimoun, Nico Shlaimoun
  • Patent number: 11704257
    Abstract: A method of provisioning a system includes defining one or more virtual peripherals such that each of the virtual peripherals corresponds to a respective device; identifying one or more enabled virtual peripherals; and identifying one or more control modules. Each of the control modules includes one or more terminals for connecting to one or more devices. The method further includes linking each of the enabled virtual peripherals to a respective terminal of the one or more control modules to form a link; generating a provisioning configuration that represents the link between the respective terminal and the corresponding one of the enabled virtual peripherals; and writing the provisioning configuration to each of the control modules. The method further includes connecting the respective device to the respective terminal consistent with the link between the respective terminal and the corresponding one of the enabled virtual peripherals.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: July 18, 2023
    Assignee: Graco Minnesota Inc.
    Inventors: Pavel V. Tysyachuk, Adriana F. Mickols, Nicholas Thomas Fritz
  • Patent number: 11693806
    Abstract: A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: July 4, 2023
    Assignee: Kioxia Corporation
    Inventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher Delaney, Leland Thompson
  • Patent number: 11682363
    Abstract: There is provided an information processing device including a voltage detection unit configured to monitor a voltage value of a signal output at a predetermined timing, and a signal control unit configured to stop output of the signal if the voltage value after a predetermined time elapses from when the voltage value detected by the voltage detection unit exceeds a first value does not exceed a second value greater than the first value.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: June 20, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Toshihide Shimuzu, Hiromasa Miyata, Junji Ohama