Abstract: The present disclosure includes apparatuses and methods related to memory with an artificial intelligence (AI) accelerator. An example apparatus can include receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode and perform AI operations using an AI accelerator based on a status of a number of register on the controller. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations (e.g., logic operations, among other operations) associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

Abstract: Systems and methods for connection virtualization in data storage device arrays are described. A host connection identifier may be determined for a storage connection request. A target storage device and corresponding completion connection identifier may be determined for a storage command including the host connection identifier. A command tracker may be stored that associates the storage command with the host connection identifier and the completion connection identifier and the storage command may be sent to the processing queue associated with the completion connection identifier.

Abstract: A technique includes holding a bus interface of a removable device that is inserted into a connector of a computer system in a state to prevent the device from communicating with a communication link. The communication link is coupled to the connector and is associated with operating system access to the device. The method includes a baseboard management controller communicating with the device using a channel other than the communication link while the bus interface of the device is held in the state; the baseboard management controller performing a security operation corresponding to the device based on the communication with the device using the channel; and the baseboard management controller releasing the bus interface of the device from the state to allow the device to communicate with the communication link in response to the baseboard management controller completing the security operation.

Abstract: A storage system comprises a storage drive that has a physical connector A and a physical connector B for connecting to the first control device and second control device, respectively. The physical connector A and physical connector B are independent access ports. The first control device is configured to access the storage drive through the physical connector A, and the second control device is configured to access the storage drive through the physical connector B.

Abstract: A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to a system memory and, accordingly, asserts a flag in the system memory. Through a write channel provided by the interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a read channel provided by the interconnect bus, without being delayed by the status checking of the flag. The host bridge controller executes a data detection command or a preset vendor command to issue a write request for programming data in a virtual address, to trigger a handshake between the host bridge controller and the system memory through the write channel. During the handshake, flag checking is achieved.

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Abstract: Composite interface circuit including bidirectional single-conductor bus, first switching circuit, and second switching circuit. Bidirectional single-conductor bus is coupled by first pull-up resistor (R1) with first direct current (“DC”) input current source having first voltage (V1). First switching circuit includes first transistor (T1) being coupled with first pull-up resistor (R1) and with bidirectional single-conductor bus. Second switching circuit includes second transistor (T2) being coupled by second pull-up resistor (R2) with second DC input current source having second voltage (V2). Second switching circuit further includes voltage divider coupling second transistor (T2) with bidirectional single-conductor bus. First and second switching circuits are respectfully configured for being coupled with first transmitter conductor (Tx1) and first receiver conductor (Rx1) of full duplex universal asynchronous data communication interface.

Abstract: The application provides an information processing device, system and method. The information processing device mainly includes a storage module and a data processing module, where the storage module is configured to receive and store input data, instruction and output data, and the input data includes one or more key features; the data processing module is configured to identify the key features included in the input data and score the input data in the storage module according to a judgment result. The information processing device, system and method provided by the application automatically scores text, pictures, audio, video, and the like instead of manually scoring, which is more accurate and faster.

Abstract: A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to the system memory and, accordingly, asserts a flag in the system memory. Through a flag reading channel provided by a interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a data reading channel provided by the interconnect bus, without being delayed by the status checking of the flag. The interconnect bus further provides a flag writing channel and a data writing channel.

Abstract: A neural network computing engine having an array of charge-trap-transistor (CTT) elements which are utilized as analog multipliers with all weight values preprogrammed into each CTT element as a CTT threshold voltage, with multiplicator values received from the neural network inference mode. The CTT elements perform computations of a fully connected (FC) neural network with each CTT element representing a neuron. Row resistors for each row of CTT element sum output currents as partial summation results. Counted pulse generators write weight values under control of a pulse generator controller. A sequential analog fabric (SAF) feeds multiple drain voltages in parallel to the CTT array to enable parallel analog computations of neurons. Partial summation results are read by an analog-to-digital converter (ADC).

Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

Abstract: A data processing board according to an embodiment of the present disclosure includes a data processing module including at least one data processing board for automatically assigning an identifier according to the voltage value measured in the internal circuit and a communication board for transmitting and receiving signal to/from the data processing board, and a data processing system including the data processing module and a monitor collecting device for selecting and parallel-processing the data received from the data processing module.

Abstract: Provided is a method of operating a neural network computing device that is configured to communicate with an external memory device and execute a plurality of layers. The method includes computing a first input address, based on first layer information of a first layer among the plurality of layers and a first memory management table, and updating the first memory management table to generate a second memory management table, reading first input data to be input to the first layer from the external memory device, based on the computed first input address, computing a first output address, based on the first layer information and the second memory management table, and updating the second memory management table to generate a third memory management table, and storing first output data output from the first layer, based on the first output address, in the external memory device.

Abstract: A memory device comprising: N cell array regions, a computation processing block suitable for generating computation-completion data by performing a network-level operation on input data, the network-level operation indicating an operation of repeating a layer-level operation M times in a loop, the layer-level operation indicating an operation of performing N neural network computations in parallel, a data operation block suitable for storing the input data and (M*N) pieces of neural network processing information in the N cell array regions, and outputting the computation-completion data through the data transfer buffer, and an operation control block suitable for controlling the computation processing block and the data operation block.

Abstract: A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.

Abstract: An FPGA upgrade method is provided, including: delivering, by a host, an upgrade instruction to an FPGA; uninstalling a PCIe driver corresponding to the FPGA to let a status of the PCIe link be changed to link down; continuously monitoring, in a first expiration time, whether the status of the PCIe link is changed to link up; and if yes, reloading the PCIe driver. The method further includes: after the FPGA receives the upgrade instruction, continuously monitoring, in a second expiration time, whether the status of the PCIe link is changed to link down, if yes, loading the configuration data from the FPGA configuration memory for upgrade; and after upgrade is completed, negotiating, by the FPGA, with the host to restore the status of the PCIe link to link up that is used for reloading the PCIe driver upon detection by the host.

Abstract: A system, method, and computer-readable medium are provided for a hardware component failure prediction system that can incorporate a time-series dimension as an input while also addressing issues related to a class imbalance problem associated with failure data. Embodiments utilize a double-stacked long short-term memory (DS-LSTM) deep neural network with a first layer of the DS-LSTM passing hidden cell states learned from a sequence of multi-dimensional parameter time steps to a second layer of the DS-LSTM that is configured to capture a next sequential prediction output. Output from the second layer is combined with a set of categorical variables to an input layer of a fully-connected dense neural network layer. Information generated by the dense neural network provides prediction of whether a hardware component will fail in a given future time interval.

Abstract: A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.

Abstract: A data storage system can organize a semiconductor memory into a first data set and a second data set with a first queue populated with a first data access request from a host. An assignment of an arbitration weight to the first queue with an arbitration circuit corresponds with the first queue being skipped during a deterministic window based on the arbitration weight.

Abstract: There is provided an information processing device including a voltage detection unit configured to monitor a voltage value of a signal output at a predetermined timing, and a signal control unit configured to stop output of the signal if the voltage value after a predetermined time elapses from when the voltage value detected by the voltage detection unit exceeds a first value does not exceed a second value greater than the first value.