Abstract: Illustrated is an I/O module which is configured for cyclically transmitting and receiving telegrams, wherein an area in which a data record can be transmitted in its entirety is provided in the telegrams, as well as an area capable of containing only a part of a data record, so that said data record is transmitted, distributed over several telegrams.

Abstract: A hardware architecture that may include: a host, a frontal engine, a parietal engine, a renderer engine, an occipital engine, a temporal engine, and a memory. The frontal engine may obtain a 5D tensor from the host and divide it into several groups of tensors. These groups of tensors may be sent or transmitted to the parietal engine, and the parietal engine may take the groups of tensors to further divide them into several tensors. The parietal engine may send these tensors to the renderer engine for execution and may send a partial amount of tensors to the occipital engine. The occipital engine may accumulate the partial amount of tensors and may execute them. The occipital engine may send the output feature as the final tensor to the temporal engine. The temporal engine may compress the final tensor before storing or saving it to the memory.

Abstract: There is provided with an information processing apparatus. A control unit controls writing of weight data to a first memory and a second memory, and controls readout of the weight data from the first memory and the second memory. The control unit further switches an operation between a first operation in which a processing unit reads out first weight data from the first memory and performs the convolution operation processing using the first weight data while the processing unit writes second weight data to the second memory in parallel, and a second operation in which the processing unit reads out the first weight data from both the first memory and the second memory and performs the convolution operation processing using the first weight data.

Abstract: An information handling system including a port or wireless antenna to operatively couple one or more peripheral devices to the information handling system and the processor executing code instructions of a peripheral devices reporting module for managing the one or more peripheral devices in coordination for a remotely-located peripheral device management system, wherein the processor is configured to generate a manifest of the information handling system and the one or more peripheral devices, and a network interface device to transmit to the remotely-located peripheral device management system the manifest to be associated a user account for peripheral device management services utilize usage data from the one or more peripheral devices to monitor peripheral device usage lifecycle status or peripheral device health status.

Abstract: The embodiments disclosed herein relate to chips used to receive and process neurological events in brain matter as captured by electrodes. Such chips may include an array of amplifiers and electrodes to receive neurological voltage signals, the chip including a config circuitry in communication with the array of amplifiers and a controller, the config circuitry configured to receive program instructions and instruct the amplifiers of a voltage threshold and instruct the controller to pass on signals from only specific rows and columns of amplifiers, the controller in communication with the array of amplifiers, the controller configured to packetize the neurological voltage signals into data packets.

Abstract: A microcontroller is provided with a plurality of slave drive units for driving peripheral devices. Individual speed units are provided that have serial shift registers, multiplexors, and duplex data communication connections with individual serial registers of respective slave drive units of a series chain. In a first cycle or mode, a serial data connection between the serial shift registers of the speed units causes data to be serially communicated, at a first relatively faster pulse rate, from the microcontroller into the data input of the series chain and to the microcontroller from the data output of the series chain. In a second cycle or mode, for each pair of single speed unit and slave drive unit, the duplex data communication between the serial shift registers of the pair causes, at a second relatively slower pulse rate, data to be serially communicated in parallel therebetween.

Abstract: A cascade extension device and a cascade system having the cascade extension device are provided. The cascade extension device includes a control module, a buffer module, a storage module, and a selecting output module. The cascade system includes a processor and a plurality of extension devices. The processor may simultaneously control the plurality of extension devices through judging the data packet received as a write command, a read command, or a bypass command by a plurality of extension devices.

Abstract: A storage device includes a reconfigurable logic circuit, a control logic circuit, and non-volatile memory. The reconfigurable logic circuit is changeable from a first accelerator to a second accelerator during an operation of the storage device. The control logic circuit is configured to receive, from the host, a host command including information about a function required by the host and dynamically reconfigure the reconfigurable logic circuit such that the reconfigurable logic circuit performs the function according to the received host command. The non-volatile memory is connected to the control logic circuit.

Abstract: A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.

Abstract: Various embodiments comprise systems, mechanisms, methods and apparatus configured to regenerate or recreate a stream of substantially continuous serial bus data traffic using stored data packet sequences representing captured energy associated with inverting and non-inverting communication lines of a differential transmission line type of serial bus (e.g., RS-422, MIL STD 1553, and the like).

Abstract: An electronic device with a connector supporting multiple connection standards includes the connector, a processor, a controller, an EDID (Extended Display Identification Data) ROM, a first multiplexer circuit and a second multiplexer circuit. The first multiplexer circuit is coupled to at least one signal pin of the connector, the processor and the controller. The second multiplexer circuit is coupled to the EDID ROM, the first multiplexer circuit, the processor and the controller. Under an update state, the controller is electrically connected to the EDID ROM through the second multiplexer circuit, and updates EDID in the EDID ROM with update data.

Abstract: The present invention relates to a modular architecture for a resilient extensible SmallSat (MARES) command and data handling (C&DH) device used in a spacecraft, the modular architecture which conforms to a 1U CubeSat board area form factor, including: a C&DH processor card disposed on a backplane of the form factor; a C&DH processor card disposed on a backplane of the form factor; a fault tolerant field programmable gate array (FPGA) disposed on the C&DH processor card, the FPGA including an embedded fault tolerant memory controller, and a soft-core processor which runs core flight software on a real-time executive for a multiprocessor operating system; and a C&DH auxiliary card disposed on the backplane and used in conjunction with the C&DH processor card, to provide processing capability for the spacecraft, the auxiliary card which contains peripheral interface drivers and read electronics for monitoring a health and safety of the spacecraft.

Abstract: A method and system for configuring a USB3 input/output port in a camera are disclosed. The method comprises responsive to an indication that a peripheral device is a non-USB3 device, remapping pins of the USB3 input/output port to a first predefined port configuration associated with an I2C protocol by remapping a RX1? pin to communicate a first I2C signal and remapping a RX1+ pin to communicate a second I2C signal, and responsive to successful authentication between the camera and the peripheral device via the I2C protocol, enabling communication with the peripheral device and remapping the pins of the USB3 input/output port to a second predefined port configuration compatible with operation of the authenticated peripheral device by remapping a TX2+ pin to communicate a first general purpose input/output signal and remapping a TX2? pin to communicate a second general purpose input/output signal.

Abstract: A variational hyper recurrent neural network (VHRNN) can be trained by, for each step in sequential training data: determining a prior probability distribution for a latent variable from a prior network of the VHRNN using an initial hidden state; determining a hidden state from a recurrent neural network (RNN) of the VHRNN using an observation state, the latent variable and the initial hidden state; determining an approximate posterior probability distribution for the latent variable from an encoder network of the VHRNN using the observation state and the initial hidden state; determining a generating probability distribution for the observation state from a decoder network of the VHRNN using the latent variable and the initial hidden state; and maximizing a variational lower bound of a marginal log-likelihood of the training data. The trained VHRNN can be used to generate sequential data.

Abstract: A marine-type communication device that reads data from a data bus, dynamically creates new data channels for a plurality of operational systems and performs a volatility assessment to determine when to save the data for transmission to a cloud network and when to transmit the data to the cloud network.

Abstract: A processing device, operatively coupled with a plurality of memory devices, is configured to receive a DMA command for a plurality of data sectors to be moved from a source memory region to a destination memory region, the destination memory region comprises a plurality of noncontiguous memory addresses and the DMA command comprises a destination value referencing the plurality of noncontiguous memory addresses. The processing device further retrieves the plurality of noncontiguous memory addresses from a location identified by the destination value. The processing device then reads the plurality of data sectors from the source memory region. The processing device also performs, for each respective data sector of the plurality of data sectors associated with the DMA command, a write operation to write the respective data sector into a corresponding respective noncontiguous memory address from the plurality of noncontiguous memory addresses of the destination memory region.

Abstract: A hybrid delta modulator that can be used as a variable threshold neuron in a neural network is described. The hybrid delta modulator exhibits a memory of the prior state of the modulator, similar to a delta modulator, and receives a sum-of-products signal from a weighting circuit and generates a quantized output stream that represents the sum-of-products signal, potentially including an activation function and offset. With appropriately selected components, the hybrid delta modulator separates the integral function of the feedback from the gain function. Further, the gain can be selected, and the characteristic of the output pattern can be tailored to include an arbitrary combination of the input and the rate of change of the input. The use of a hybrid delta modulator of the present approach provides a simpler solution and better performance than many prior art neurons.

Abstract: A processing device, operatively coupled with a memory component, is configured to provide a plurality of virtual memory controllers and to provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The processing device further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, wherein each of the plurality of physical functions corresponds to a different virtual machine running on the host computing system, and manages input/output (IO) operations received from the host computing systems and directed to the plurality of physical functions, as well as background operations performed on the memory component, in view of class of service parameters associated with the plurality of physical functions.

Abstract: The disclosure relates to a controller and a transceiver and associated software and methods.

Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.