Abstract: A device for use in a building management system (BMS) includes a base hardware component that provides communication between the equipment and a first network associated with the BMS. The base hardware component includes a processor and a memory. The device further includes a modular hardware component connected to the base hardware component and a modular software component stored in the memory that recognizes the modular hardware component connected to the base hardware component and provides communication between the equipment and a second network using the modular hardware component. The processor executes a control application to control operation of the equipment based in part on data received from the equipment and data received from at least one of the first network and the second network.

Abstract: The present disclosure describes apparatuses and methods for artificial intelligence-enabled management of storage media. In some aspects, a media access manager of a storage media system receives, from a host system, host input/output commands (I/Os) for access to storage media of the storage media system. The media access manager provides information describing the host I/Os to an artificial intelligence engine and receives, from the artificial intelligence engine, a prediction of host system behavior with respect to subsequent access of the storage media. The media access manager then schedules, based on the prediction of host system behavior, the host I/Os for access to the storage media of the storage system. By so doing, the host I/Os may be scheduled to optimize host system access of the storage media, such as to avoid conflict with internal I/Os of the storage system or preempt various thresholds based on upcoming idle time.

Abstract: A programmable logic controller performs execution of a program in each set period and repeats the execution of the program. The first device storage stores a device value that is an input value and an output value of the program. The second device storage stores the device value stored in the first device storage in a previous period. In a case in which a reading target preset for a device designated by a monitor request received from an engineering tool is the first device storage, the command processor reads the device value stored in the first device storage after execution of the program in a current period is completed, and in a case in which the reading target is the second device storage, the command processor immediately reads the device value stored in the second device storage. The command transmission/reception element transmits the device value to the engineering tool.

Abstract: A serial transmission system includes a first storage circuit, a second storage circuit, a control circuit, and a serial processing circuit. The first storage circuit is configured to store data-to-be-transmitted of a plurality of users. The second storage circuit is coupled to the first storage circuit. The control circuit is configured to control the second storage circuit to receive the data-to-be-transmitted from the first storage circuit. The serial processing circuit is configured to receive the data-to-be-transmitted from the second storage circuit in series, and output a plurality of multi-user packets.

Abstract: Technologies for latency based service level agreement (SLA) management in remote direct memory access (RDMA) networks include multiple compute devices in communication via a network switch. A compute device determines a service level objective (SLO) indicative of a guaranteed maximum latency for a percentage of RDMA requests of an RDMA session. The compute device receives latency data indicative of latency of an RDMA request from a host device. The compute device determines a priority associated with the RDMA request as a function of the SLO and the latency data. The compute device schedules the RDMA request based on the priority. The network switch may allocate queue resources to the RDMA request based on the priority, reclaim the queue resources after the RDMA request is scheduled, and then return the queue resources to a free pool. Other embodiments are described and claimed.

Abstract: Systems, apparatuses, and methods for controlling bandwidth through shared transaction limits are described. An apparatus includes at least a plurality of agents, a plurality of transaction-limit (T-Limit) nodes, a T-Limit manager, and one or more endpoints. The T-Limit manager creates a plurality of credits for the plurality of agents to send transactions to a given endpoint. Then, the T-Limit manager partitions the credits into N+1 portions for N agents, wherein the extra N+1 portion is a shared pool for use by agents when they run out of their private credits. The T-Limit manager assigns a separate private portion of the N portions to the N agents for use by only the corresponding agent. When an agent runs out of private credits, the agent's T-Limit node sends a request to the T-Limit manager for credits from the shared pool.

Abstract: To automate processing of agent software which operates in a storage apparatus. A storage system includes: a storage apparatus including a storage device which stores data and one or two or more pieces of agent software, and a controller for controlling the agent software; and a server that transmits and receives information to and from the storage apparatus via a network, wherein the controller: activates the agent software and monitors a status of the agent software; and causes the agent software to execute processing on condition that the status of the agent software is standby.

Abstract: Methods, systems, and computer program products for high-performance cluster computing. Multiple components are operatively interconnected to carry out operations for high-performance RDMA I/O transfers over an RDMA NIC. A virtual machine of a virtualization environment initiates a first I/O call to an HCI storage pool controller using RDMA. Responsive to the first I/O call, a second I/O call is initiated from the HCI storage pool controller to a storage device of an HCI storage pool. The first I/O call to the HCI storage pool controller is implemented through a first virtual function of an RDMA NIC that is exposed in the user space of the virtualization environment. Prior to the first RDMA I/O call, a contiguous unit of memory to use in an RDMA I/O transfer is registered with the RDMA NIC. The contiguous unit of memory comprises memory that is registered using non-RDMA paths such as TCP or iSCSI.

Abstract: A system and method for input/output communication is disclosed. In one embodiment, a virtual device identifies a queue including a plurality of input/output (I/O) descriptors, each of the plurality of I/O descriptors representing one of: an active descriptor associated with an active I/O request or an executed descriptor that is associated with an executed I/O request. The virtual device retrieves, from a first index in the queue, one or more active descriptors associated with an I/O request. The virtual device executes the I/O request. The virtual device writes a first executed descriptor to a second index in the queue, where the first executed descriptor indicates the I/O request has been executed. The virtual device updates the second index to an initial position in the queue responsive to a predetermined condition.

Abstract: A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

Abstract: A system for controlling a motor with a plurality of motor control functions including at least a current control loop and a velocity control loop. The system includes one of a hybrid Digital Signal Processor (DSP)-Field Programmable Gate Array (FPGA) architecture having an integral DSP and an integral FPGA or a System on a Chip (SoC) architecture having a Microcontroller Sub-System (MSS) and an FPGA fabric. The current control loop function is assigned to the integral FPGA for the hybrid DSP-FPGA architecture, and at least the velocity control loop function is assigned to the DSP the hybrid DSP-FPGA architecture. Alternatively, the current control loop function is assigned the FPGA fabric of the SoC architecture, and at least the velocity control loop function is assigned to the MSS of the SoC architecture.

Abstract: An information handling system may include a motherboard and a floating paddle card. The motherboard may include a host system comprising a host system processor, a logic device configured to perform a functionality of the information handling system in accordance with code stored on non-transitory computer-readable media of the logic device, and a management controller communicatively coupled to the host system processor and the logic device and configured to perform out-of-band management of the information handling system. The floating paddle card may be communicatively coupled to the motherboard and configured to serve as interface between one or more devices coupled to the floating paddle card and the logic device and the management controller, the floating paddle card comprising a microcontroller unit configured to, alone or in combination with other circuitry of the floating paddle card, divide management of the one or more devices between the motherboard and the floating paddle card.

Abstract: A peripheral circuit includes a data preparation circuit, configured to selectively import, to a row or column of the resistive random access memory (RRAM) crossbar array based on a first control signal, preprocessed data obtained by first preprocessing on first data that is input into the data preparation circuit, a data selection circuit, configured to selectively export second data from the row or column of the RRAM crossbar array based on a second control signal, and perform second preprocessing on the second data to obtain third data, a data reading circuit, configured to: perform a weight update control operation, and perform a max pooling operation on fourth data that is input into the data reading circuit, to obtain fifth data, and a reverse training computation circuit, configured to calculate an error and a derivative of sixth data that is input into the reverse training computation circuit.

Abstract: A memory system including a storage device and a memory controller controlling the storage device and decoding an encoded data. The memory controller including: a history buffer storing a decoded data string; a history buffer read controller executing a read request to the history buffer; a decode executing section generating a first shaped data string based on the decoded data string read from the history buffer, generating a second shaped data string by referring the first shaped data string before the first shaped data string being written back to the history buffer in response to the read request, and generating a decoded result using the first shaped data string and the second shaped data string.

Abstract: An information handling system includes a processor, a plurality of dual in-line memory modules (DIMMs), and a basic input/output system (BIOS). During a power-on self-test (POST), the BIOS may read serial presence detect data from each of the DIMMs, determine a total amount of installed memory. The BIOS may determine whether the total amount of the installed memory exceeds a maximum memory capacity of the processor. If so, the BIOS may remove memory capacity of the DIMMs to create a second total amount of the installed memory that is less than the maximum memory capacity of the processor, configure a memory address decode register with the second total amount of the installed memory, and complete the POST.

Abstract: Calibrating devices communicating on the shared bus can assist in reducing conflicts on the bus and the resulting loss of data. For example, the timing of transmission of data from one device to another device on the shared bus may be adjusted to compensate for delays on the shared bus. For example, the transmitting device may adjust transmission to an earlier time than the programmed time by an amount proportional to a known delay, such that the signal arrives at a receiving device at the programmed time. When the adjustment is not able to obtain a desired alignment or would cause conflicts on the shared data bus, the timing may be adjusted to delay the transmission, rather than advance the transmission, such that the adjusted transmission time results in the receipt of the signal at the receiving device in an unused time window after the programmed time.

Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

Abstract: In one example, an apparatus includes: a radio frequency (RF) receiver to receive an RF signal; a media access control (MAC) circuit to receive data and output MAC-processed data according to a clock signal that is phase delayed with respect to a source clock signal when the RF receiver is active; and an interference mitigation circuit to receive the MAC-processed data and provide the MAC-processed data to a physical circuit resynchronized to the source clock signal.

Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.