Patents Examined by Ginette Peralta
  • Patent number: 8003481
    Abstract: A method for forming an HSG (hemispherical grain) layer on a storage electrode of a capacitor formed on a substrate is provided. The method includes a step of introducing a source gas into a reacting chamber to deposit a small amount of HSG nuclei on a conductive layer pattern of a capacitor electrode during a step of stabilizing the substrate temperature. After the substrate temperature is stabilized, a larger amount of source gas is introduced into the chamber to form additional HSG nuclei. Thereafter, a step of annealing is performed to form the HSG layer.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: August 23, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Dong Kang, Chang-seog Ko, Seung-jin Lee, Kyoung-Bok Lee
  • Patent number: 7126222
    Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: October 24, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yusuke Harada
  • Patent number: 7064374
    Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: June 20, 2006
    Assignee: Symetrix Corporation
    Inventors: Narayan Solayappan, Jolanta Celinska, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 7053482
    Abstract: A ceramic package with a lid attached thereon, which has radiating grooves at its upper surface and/or lower surface to radiate heat generated from a chip-type device is disclosed. The ceramic package includes a laminated ceramic substrate comprised of a plurality of ceramic substrate such that a cavity is centrally defined in the laminated ceramic substrate, a chip-type device mounted on the bottom of the cavity of the laminated ceramic substrate, and a lid attached to the top of the laminated ceramic substrate to close the cavity, which is provided at its upper and/or lower surface with protrusions to efficiently radiate heat generated from the chip-type device.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 30, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Seong Won Cho
  • Patent number: 7053401
    Abstract: Soluble, photosensitive precursors of pentacene are synthesized by a one-step Diels-Alder reaction of pentacene with N-sulfinylamides. These precursors may include a photopolymerizable group, which renders the pentacene precursor as a negative tone resist. The pentacene precursor may also include an acid-sensitive protecting group, which in the presence of a photoacid generator and upon exposure to UV light, is removed and the product becomes base soluble. Patterned pentacene thin films may be obtained by exposure to UV light through a mask and/or heating, and used as an active channel material for an organic field effect transistor.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 30, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali Ardakani, Christos D. Dimitrakopoulos, Teresita O. Graham, David R. Medeiros
  • Patent number: 7026238
    Abstract: Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: April 11, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Ming Xi, Paul Frederick Smith, Ling Chen, Michael X. Yang, Mei Chang, Fusen Chen, Christophe Marcadal, Jenny C. Lin
  • Patent number: 7022559
    Abstract: An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type. In a particular embodiment, an integrated circuit includes an n-channel FET having a tantalum-based gate electrode with a work function approximately the same as n-doped polysilicon, and a p-channel FET has a tantalum nitride-based gate electrode with a work function approximately the same as p-doped polysilicon.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: John P. Barnak, Robert S. Chau, Chunlin Liang
  • Patent number: 7015562
    Abstract: A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity. Dopant concentrations range from 1×1017 to 3×1018 dopant atoms per cm3 for the anode emitter, especially on its surface 1019 dopant atoms per cm3 or more for the cathode emitter and approximately 1016 dopant atoms per cm3 for the blocking function of an anode-side zone.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: March 21, 2006
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Alfred Porst
  • Patent number: 7001829
    Abstract: In a method of manufacturing a semiconductor device, a laser beam capable of irradiating a large area in one shot is irradiated to an amorphous silicon film into which a catalytic element is intentionally introduced to crystallize the amorphous silicon film, thus obtaining a crystalline silicon film.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: February 21, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6995069
    Abstract: In a method for manufacturing a semiconductor storage device having a dielectric capacitor, an IrO2 film, an Ir film, an amorphous film, and a Pt film—are sequentially made on an Si substrate. The SBT film may comprise Bix, Sry, Ta2.0 and Oz, where the atomic ratio may be within the range of 0?Sr/Ti?1.0, 0?Ba/Ti?1.0. The Pt film, the amorphous film, the Ir film, and the IrO2 film formed into a dielectric capacitor and the amorphous film is twice annealed to change its amorphous phase to a fluorite phase and then to a crystal phase of a perovskite type crystalline structure and thereby obtain the SBT film. The process may include a lower electrode made from an organic metal source material selected from a group consisting of Bi(C6H5)3, Bi(o-C7H7)3, Bi(O—C2H5)3, Bi(O—iC3H7)3, Bi(O-tC4H9)3, Bi(O-tC5H11)3, Sr(THD)2, Sr(THD)2 tetraglyme, Sr(Me5C5)2. 2THF, Ti(i-OC3H7)4, TiO(THD)2, Ti(TD)2(i-OC3H7)2, Ta(i-OC3H7)5, Ta(iOC3H7)4THD, Nb(i-OC3H7)5, Nb(i-OC3H7)4THD.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: February 7, 2006
    Assignee: Sony Corporation
    Inventors: Katsuyuki Hironaka, Masataka Sugiyama, Chiharu Isobe, Takaaki Ami
  • Patent number: 6992391
    Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventors: Andrew Ott, Lawrence Wong, Patrick Morrow, Jihperng Leu, Grant M. Kloster
  • Patent number: 6982215
    Abstract: A method for using ion implantation to implant phosphorous or arsenic impurities into shallow source/drain regions or into polysilicon electrodes used in devices having shallow source/drain electrodes. A phosphorous source having an abundance of P2+ ions is used in an ion beam system adjusted to select P2+ ions. Since each ion contains two phosphorous atoms the ion beam requires twice the beam energy and half the beam density. This provides good wafer throughput and improved source life. An arsenic source having an abundance of As2+ ions can be substituted for the solid phosphorous source resulting in a beam of As2+ ions.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: January 3, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Buan Heng Lee, Teck Hong Low, Hai Rong Wang, Tang Ying, Zadig Cherng-Ching Lam
  • Patent number: 6969905
    Abstract: A leadframe for semiconductor chips and electronic devices produced on the leadframe includes providing the leadframe with a basic substrate, on which are disposed external contact elements exhibiting a rivet-shaped cross-section with a rivet head region, a rivet shank region, and a rivet foot region, as a result of which, the external contact elements are securely anchored in the housing made of a plastics compound.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: November 29, 2005
    Assignee: Infineon Technologies AG
    Inventor: Stefan Paulus
  • Patent number: 6964929
    Abstract: A method of making a semiconductor structure includes trimming a patterned hard mask with a wet etch, wherein the hard mask is on a gate layer; and etching the gate layer. In making multiple structures on a semiconductor wafer, an average width of lines in the patterned hard mask is trimmed by at least 100 ?.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: November 15, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sundar Narayanan, Chidambaram Kallingal
  • Patent number: 6951824
    Abstract: A method for manufacturing a micromechanical component, that has at least one hollow space and a functional element that is provided at least partially in the hollow space and/or a functional layer that is provided at least partially therein, and a micromechanical component that is manufactured in accordance with the method, are described. To reduce manufacturing costs, the functional element and/or the functional layer is provided with a first protective layer at least in an area that directly or indirectly borders on a first sacrificial layer, which temporarily occupies the space of the hollow space that is subsequently formed in one or a plurality of etching steps, the material of the first protective layer being selected such that at least one etching process and/or etching medium, which etches or dissolves the first sacrificial layer, either does not substantially attack the first protective layer or does so only at a reduced etching rate in comparison to the first sacrificial layer.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: October 4, 2005
    Assignee: Robert Bosch GmbH
    Inventors: Frank Fischer, Peter Hein, Eckhard Graf
  • Patent number: 6942318
    Abstract: A chamber includes a substrate, a chamber layer disposed on the substrate that defines the sidewalls of the chamber, and the chamber layer has a chamber surface. The chamber has an area in the plane formed by the chamber surface in the range from about 1 square micrometer to about 10,000 square micrometers. The chamber also includes an orifice layer disposed over the chamber layer. The orifice layer has a first and second orifice surface and a bore wherein the bore has an area in the plane formed by the first orifice surface less than the chamber area. The chamber further includes a protective layer deposited, through the bore, on the sidewalls of the chamber layer and a portion of the first orifice surface.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: September 13, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Arjang Fartash
  • Patent number: 6943448
    Abstract: The present invention is directed to a structure comprised of alternating layers of metal and sacrificial material built up using standard CMOS processing techniques, a process for building such a structure, a process for fabricating devices from such a structure, and the devices fabricated from such a structure. In one embodiment, a first metal layer is carried by a substrate. A first sacrificial layer is carried by the first metal layer. A second metal layer is carried by the sacrificial layer. The second metal layer has a portion forming a micro-machined metal mesh. When the portion of the first sacrificial layer in the area of the micro-machined metal mesh is removed, the micro-machined metal mesh is released and suspended above the first metal layer a height determined by the thickness of the first sacrificial layer. The structure may be varied by providing a base layer of sacrificial material between the surface of the substrate and the first metal layer.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: September 13, 2005
    Assignee: Akustica, Inc.
    Inventors: Kaigham J. Gabriel, Xu Zhu
  • Patent number: 6939800
    Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventors: Hong-Qiang Lu, Peter A. Burke, Wilbur G. Catabay
  • Patent number: 6940124
    Abstract: Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of ?4 to ?3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: September 6, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidehito Kitakado, Masahiko Hayakawa, Shunpei Yamazaki, Taketomi Asami
  • Patent number: 6939789
    Abstract: The invention includes a method of wafer level chip scale packaging including providing a semiconductor device having a silicon based substrate with discrete devices defined therein and a contact pad near an upper surface thereof, a passivation layer overlying the silicon based substrate and the contact pad, and the passivation layer having an opening therein exposing at least a portion of the contact pad, and a redistribution trace electrically connected to the contact pad near a first end and having a second end of spaced a distance from the contact pad. Forming an encapsulation layer over the semiconductor device including the redistribution trace. Forming an opening in the encapsulation layer down to the redistribution trace. Forming a contact post in the opening in the encapsulation layer, and the contact post having a first end electrically connected to the redistribution trace and a second exposed end.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: September 6, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chender Huang, Pei-Haw Tsao, Jones Wang, Ken Chen